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beb7dd86a1
Fix the misspellings of "propogate", "writting" and (oh, the shame :-) "kenrel" in the source tree. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
765 lines
20 KiB
C
765 lines
20 KiB
C
/*
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* Cell Broadband Engine OProfile Support
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*
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* (C) Copyright IBM Corporation 2006
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*
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* Author: David Erb (djerb@us.ibm.com)
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* Modifications:
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* Carl Love <carll@us.ibm.com>
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* Maynard Johnson <maynardj@us.ibm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/jiffies.h>
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#include <linux/kthread.h>
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#include <linux/oprofile.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <asm/cell-pmu.h>
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#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/io.h>
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#include <asm/oprofile_impl.h>
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#include <asm/processor.h>
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#include <asm/prom.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#include <asm/rtas.h>
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#include <asm/system.h>
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#include "../platforms/cell/interrupt.h"
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#include "../platforms/cell/cbe_regs.h"
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#define PPU_CYCLES_EVENT_NUM 1 /* event number for CYCLES */
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#define PPU_CYCLES_GRP_NUM 1 /* special group number for identifying
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* PPU_CYCLES event
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*/
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#define CBE_COUNT_ALL_CYCLES 0x42800000 /* PPU cycle event specifier */
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#define NUM_THREADS 2 /* number of physical threads in
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* physical processor
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*/
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#define NUM_TRACE_BUS_WORDS 4
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#define NUM_INPUT_BUS_WORDS 2
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struct pmc_cntrl_data {
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unsigned long vcntr;
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unsigned long evnts;
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unsigned long masks;
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unsigned long enabled;
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};
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/*
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* ibm,cbe-perftools rtas parameters
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*/
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struct pm_signal {
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u16 cpu; /* Processor to modify */
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u16 sub_unit; /* hw subunit this applies to (if applicable) */
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short int signal_group; /* Signal Group to Enable/Disable */
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u8 bus_word; /* Enable/Disable on this Trace/Trigger/Event
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* Bus Word(s) (bitmask)
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*/
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u8 bit; /* Trigger/Event bit (if applicable) */
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};
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/*
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* rtas call arguments
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*/
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enum {
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SUBFUNC_RESET = 1,
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SUBFUNC_ACTIVATE = 2,
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SUBFUNC_DEACTIVATE = 3,
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PASSTHRU_IGNORE = 0,
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PASSTHRU_ENABLE = 1,
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PASSTHRU_DISABLE = 2,
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};
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struct pm_cntrl {
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u16 enable;
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u16 stop_at_max;
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u16 trace_mode;
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u16 freeze;
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u16 count_mode;
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};
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static struct {
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u32 group_control;
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u32 debug_bus_control;
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struct pm_cntrl pm_cntrl;
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u32 pm07_cntrl[NR_PHYS_CTRS];
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} pm_regs;
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#define GET_SUB_UNIT(x) ((x & 0x0000f000) >> 12)
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#define GET_BUS_WORD(x) ((x & 0x000000f0) >> 4)
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#define GET_BUS_TYPE(x) ((x & 0x00000300) >> 8)
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#define GET_POLARITY(x) ((x & 0x00000002) >> 1)
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#define GET_COUNT_CYCLES(x) (x & 0x00000001)
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#define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
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static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
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static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
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/* Interpetation of hdw_thread:
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* 0 - even virtual cpus 0, 2, 4,...
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* 1 - odd virtual cpus 1, 3, 5, ...
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*/
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static u32 hdw_thread;
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static u32 virt_cntr_inter_mask;
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static struct timer_list timer_virt_cntr;
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/* pm_signal needs to be global since it is initialized in
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* cell_reg_setup at the time when the necessary information
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* is available.
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*/
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static struct pm_signal pm_signal[NR_PHYS_CTRS];
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static int pm_rtas_token;
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static u32 reset_value[NR_PHYS_CTRS];
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static int num_counters;
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static int oprofile_running;
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static DEFINE_SPINLOCK(virt_cntr_lock);
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static u32 ctr_enabled;
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static unsigned char trace_bus[NUM_TRACE_BUS_WORDS];
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static unsigned char input_bus[NUM_INPUT_BUS_WORDS];
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/*
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* Firmware interface functions
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*/
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static int
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rtas_ibm_cbe_perftools(int subfunc, int passthru,
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void *address, unsigned long length)
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{
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u64 paddr = __pa(address);
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return rtas_call(pm_rtas_token, 5, 1, NULL, subfunc, passthru,
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paddr >> 32, paddr & 0xffffffff, length);
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}
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static void pm_rtas_reset_signals(u32 node)
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{
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int ret;
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struct pm_signal pm_signal_local;
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/* The debug bus is being set to the passthru disable state.
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* However, the FW still expects atleast one legal signal routing
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* entry or it will return an error on the arguments. If we don't
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* supply a valid entry, we must ignore all return values. Ignoring
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* all return values means we might miss an error we should be
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* concerned about.
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*/
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/* fw expects physical cpu #. */
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pm_signal_local.cpu = node;
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pm_signal_local.signal_group = 21;
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pm_signal_local.bus_word = 1;
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pm_signal_local.sub_unit = 0;
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pm_signal_local.bit = 0;
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ret = rtas_ibm_cbe_perftools(SUBFUNC_RESET, PASSTHRU_DISABLE,
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&pm_signal_local,
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sizeof(struct pm_signal));
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if (ret)
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printk(KERN_WARNING "%s: rtas returned: %d\n",
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__FUNCTION__, ret);
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}
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static void pm_rtas_activate_signals(u32 node, u32 count)
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{
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int ret;
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int i, j;
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struct pm_signal pm_signal_local[NR_PHYS_CTRS];
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/* There is no debug setup required for the cycles event.
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* Note that only events in the same group can be used.
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* Otherwise, there will be conflicts in correctly routing
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* the signals on the debug bus. It is the responsiblity
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* of the OProfile user tool to check the events are in
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* the same group.
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*/
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i = 0;
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for (j = 0; j < count; j++) {
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if (pm_signal[j].signal_group != PPU_CYCLES_GRP_NUM) {
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/* fw expects physical cpu # */
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pm_signal_local[i].cpu = node;
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pm_signal_local[i].signal_group
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= pm_signal[j].signal_group;
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pm_signal_local[i].bus_word = pm_signal[j].bus_word;
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pm_signal_local[i].sub_unit = pm_signal[j].sub_unit;
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pm_signal_local[i].bit = pm_signal[j].bit;
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i++;
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}
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}
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if (i != 0) {
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ret = rtas_ibm_cbe_perftools(SUBFUNC_ACTIVATE, PASSTHRU_ENABLE,
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pm_signal_local,
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i * sizeof(struct pm_signal));
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if (ret)
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printk(KERN_WARNING "%s: rtas returned: %d\n",
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__FUNCTION__, ret);
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}
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}
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/*
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* PM Signal functions
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*/
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static void set_pm_event(u32 ctr, int event, u32 unit_mask)
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{
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struct pm_signal *p;
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u32 signal_bit;
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u32 bus_word, bus_type, count_cycles, polarity, input_control;
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int j, i;
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if (event == PPU_CYCLES_EVENT_NUM) {
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/* Special Event: Count all cpu cycles */
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pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
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p = &(pm_signal[ctr]);
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p->signal_group = PPU_CYCLES_GRP_NUM;
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p->bus_word = 1;
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p->sub_unit = 0;
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p->bit = 0;
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goto out;
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} else {
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pm_regs.pm07_cntrl[ctr] = 0;
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}
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bus_word = GET_BUS_WORD(unit_mask);
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bus_type = GET_BUS_TYPE(unit_mask);
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count_cycles = GET_COUNT_CYCLES(unit_mask);
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polarity = GET_POLARITY(unit_mask);
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input_control = GET_INPUT_CONTROL(unit_mask);
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signal_bit = (event % 100);
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p = &(pm_signal[ctr]);
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p->signal_group = event / 100;
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p->bus_word = bus_word;
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p->sub_unit = (unit_mask & 0x0000f000) >> 12;
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pm_regs.pm07_cntrl[ctr] = 0;
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
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/* Some of the islands signal selection is based on 64 bit words.
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* The debug bus words are 32 bits, the input words to the performance
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* counters are defined as 32 bits. Need to convert the 64 bit island
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* specification to the appropriate 32 input bit and bus word for the
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* performance counter event selection. See the CELL Performance
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* monitoring signals manual and the Perf cntr hardware descriptions
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* for the details.
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*/
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if (input_control == 0) {
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if (signal_bit > 31) {
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signal_bit -= 32;
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if (bus_word == 0x3)
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bus_word = 0x2;
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else if (bus_word == 0xc)
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bus_word = 0x8;
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}
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if ((bus_type == 0) && p->signal_group >= 60)
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bus_type = 2;
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if ((bus_type == 1) && p->signal_group >= 50)
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bus_type = 0;
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
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} else {
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pm_regs.pm07_cntrl[ctr] = 0;
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p->bit = signal_bit;
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}
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for (i = 0; i < NUM_TRACE_BUS_WORDS; i++) {
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if (bus_word & (1 << i)) {
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pm_regs.debug_bus_control |=
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(bus_type << (31 - (2 * i) + 1));
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for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
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if (input_bus[j] == 0xff) {
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input_bus[j] = i;
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pm_regs.group_control |=
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(i << (31 - i));
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break;
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}
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}
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}
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}
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out:
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;
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}
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static void write_pm_cntrl(int cpu)
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{
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/* Oprofile will use 32 bit counters, set bits 7:10 to 0
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* pmregs.pm_cntrl is a global
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*/
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u32 val = 0;
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if (pm_regs.pm_cntrl.enable == 1)
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val |= CBE_PM_ENABLE_PERF_MON;
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if (pm_regs.pm_cntrl.stop_at_max == 1)
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val |= CBE_PM_STOP_AT_MAX;
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if (pm_regs.pm_cntrl.trace_mode == 1)
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val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
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if (pm_regs.pm_cntrl.freeze == 1)
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val |= CBE_PM_FREEZE_ALL_CTRS;
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/* Routine set_count_mode must be called previously to set
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* the count mode based on the user selection of user and kernel.
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*/
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val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);
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cbe_write_pm(cpu, pm_control, val);
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}
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static inline void
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set_count_mode(u32 kernel, u32 user)
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{
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/* The user must specify user and kernel if they want them. If
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* neither is specified, OProfile will count in hypervisor mode.
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* pm_regs.pm_cntrl is a global
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*/
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if (kernel) {
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if (user)
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pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;
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else
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pm_regs.pm_cntrl.count_mode =
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CBE_COUNT_SUPERVISOR_MODE;
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} else {
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if (user)
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pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;
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else
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pm_regs.pm_cntrl.count_mode =
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CBE_COUNT_HYPERVISOR_MODE;
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}
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}
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static inline void enable_ctr(u32 cpu, u32 ctr, u32 * pm07_cntrl)
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{
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pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
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cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
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}
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/*
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* Oprofile is expected to collect data on all CPUs simultaneously.
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* However, there is one set of performance counters per node. There are
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* two hardware threads or virtual CPUs on each node. Hence, OProfile must
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* multiplex in time the performance counter collection on the two virtual
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* CPUs. The multiplexing of the performance counters is done by this
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* virtual counter routine.
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*
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* The pmc_values used below is defined as 'per-cpu' but its use is
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* more akin to 'per-node'. We need to store two sets of counter
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* values per node -- one for the previous run and one for the next.
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* The per-cpu[NR_PHYS_CTRS] gives us the storage we need. Each odd/even
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* pair of per-cpu arrays is used for storing the previous and next
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* pmc values for a given node.
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* NOTE: We use the per-cpu variable to improve cache performance.
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*/
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static void cell_virtual_cntr(unsigned long data)
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{
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/* This routine will alternate loading the virtual counters for
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* virtual CPUs
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*/
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int i, prev_hdw_thread, next_hdw_thread;
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u32 cpu;
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unsigned long flags;
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/* Make sure that the interrupt_hander and
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* the virt counter are not both playing with
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* the counters on the same node.
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*/
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spin_lock_irqsave(&virt_cntr_lock, flags);
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prev_hdw_thread = hdw_thread;
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/* switch the cpu handling the interrupts */
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hdw_thread = 1 ^ hdw_thread;
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next_hdw_thread = hdw_thread;
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for (i = 0; i < num_counters; i++)
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/* There are some per thread events. Must do the
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* set event, for the thread that is being started
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*/
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set_pm_event(i,
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pmc_cntrl[next_hdw_thread][i].evnts,
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pmc_cntrl[next_hdw_thread][i].masks);
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/* The following is done only once per each node, but
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* we need cpu #, not node #, to pass to the cbe_xxx functions.
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*/
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for_each_online_cpu(cpu) {
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if (cbe_get_hw_thread_id(cpu))
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continue;
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/* stop counters, save counter values, restore counts
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* for previous thread
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*/
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cbe_disable_pm(cpu);
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cbe_disable_pm_interrupts(cpu);
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for (i = 0; i < num_counters; i++) {
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per_cpu(pmc_values, cpu + prev_hdw_thread)[i]
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= cbe_read_ctr(cpu, i);
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if (per_cpu(pmc_values, cpu + next_hdw_thread)[i]
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== 0xFFFFFFFF)
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/* If the cntr value is 0xffffffff, we must
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* reset that to 0xfffffff0 when the current
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* thread is restarted. This will generate a
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* new interrupt and make sure that we never
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* restore the counters to the max value. If
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* the counters were restored to the max value,
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* they do not increment and no interrupts are
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* generated. Hence no more samples will be
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* collected on that cpu.
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*/
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cbe_write_ctr(cpu, i, 0xFFFFFFF0);
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else
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cbe_write_ctr(cpu, i,
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per_cpu(pmc_values,
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cpu +
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next_hdw_thread)[i]);
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}
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/* Switch to the other thread. Change the interrupt
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* and control regs to be scheduled on the CPU
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* corresponding to the thread to execute.
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*/
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for (i = 0; i < num_counters; i++) {
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if (pmc_cntrl[next_hdw_thread][i].enabled) {
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/* There are some per thread events.
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* Must do the set event, enable_cntr
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* for each cpu.
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*/
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enable_ctr(cpu, i,
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pm_regs.pm07_cntrl);
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} else {
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cbe_write_pm07_control(cpu, i, 0);
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}
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}
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/* Enable interrupts on the CPU thread that is starting */
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cbe_enable_pm_interrupts(cpu, next_hdw_thread,
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virt_cntr_inter_mask);
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cbe_enable_pm(cpu);
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}
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spin_unlock_irqrestore(&virt_cntr_lock, flags);
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mod_timer(&timer_virt_cntr, jiffies + HZ / 10);
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}
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static void start_virt_cntrs(void)
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{
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init_timer(&timer_virt_cntr);
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timer_virt_cntr.function = cell_virtual_cntr;
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timer_virt_cntr.data = 0UL;
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timer_virt_cntr.expires = jiffies + HZ / 10;
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add_timer(&timer_virt_cntr);
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}
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/* This function is called once for all cpus combined */
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static void
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cell_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys, int num_ctrs)
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{
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int i, j, cpu;
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pm_rtas_token = rtas_token("ibm,cbe-perftools");
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if (pm_rtas_token == RTAS_UNKNOWN_SERVICE) {
|
|
printk(KERN_WARNING "%s: RTAS_UNKNOWN_SERVICE\n",
|
|
__FUNCTION__);
|
|
goto out;
|
|
}
|
|
|
|
num_counters = num_ctrs;
|
|
|
|
pm_regs.group_control = 0;
|
|
pm_regs.debug_bus_control = 0;
|
|
|
|
/* setup the pm_control register */
|
|
memset(&pm_regs.pm_cntrl, 0, sizeof(struct pm_cntrl));
|
|
pm_regs.pm_cntrl.stop_at_max = 1;
|
|
pm_regs.pm_cntrl.trace_mode = 0;
|
|
pm_regs.pm_cntrl.freeze = 1;
|
|
|
|
set_count_mode(sys->enable_kernel, sys->enable_user);
|
|
|
|
/* Setup the thread 0 events */
|
|
for (i = 0; i < num_ctrs; ++i) {
|
|
|
|
pmc_cntrl[0][i].evnts = ctr[i].event;
|
|
pmc_cntrl[0][i].masks = ctr[i].unit_mask;
|
|
pmc_cntrl[0][i].enabled = ctr[i].enabled;
|
|
pmc_cntrl[0][i].vcntr = i;
|
|
|
|
for_each_possible_cpu(j)
|
|
per_cpu(pmc_values, j)[i] = 0;
|
|
}
|
|
|
|
/* Setup the thread 1 events, map the thread 0 event to the
|
|
* equivalent thread 1 event.
|
|
*/
|
|
for (i = 0; i < num_ctrs; ++i) {
|
|
if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))
|
|
pmc_cntrl[1][i].evnts = ctr[i].event + 19;
|
|
else if (ctr[i].event == 2203)
|
|
pmc_cntrl[1][i].evnts = ctr[i].event;
|
|
else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))
|
|
pmc_cntrl[1][i].evnts = ctr[i].event + 16;
|
|
else
|
|
pmc_cntrl[1][i].evnts = ctr[i].event;
|
|
|
|
pmc_cntrl[1][i].masks = ctr[i].unit_mask;
|
|
pmc_cntrl[1][i].enabled = ctr[i].enabled;
|
|
pmc_cntrl[1][i].vcntr = i;
|
|
}
|
|
|
|
for (i = 0; i < NUM_TRACE_BUS_WORDS; i++)
|
|
trace_bus[i] = 0xff;
|
|
|
|
for (i = 0; i < NUM_INPUT_BUS_WORDS; i++)
|
|
input_bus[i] = 0xff;
|
|
|
|
/* Our counters count up, and "count" refers to
|
|
* how much before the next interrupt, and we interrupt
|
|
* on overflow. So we calculate the starting value
|
|
* which will give us "count" until overflow.
|
|
* Then we set the events on the enabled counters.
|
|
*/
|
|
for (i = 0; i < num_counters; ++i) {
|
|
/* start with virtual counter set 0 */
|
|
if (pmc_cntrl[0][i].enabled) {
|
|
/* Using 32bit counters, reset max - count */
|
|
reset_value[i] = 0xFFFFFFFF - ctr[i].count;
|
|
set_pm_event(i,
|
|
pmc_cntrl[0][i].evnts,
|
|
pmc_cntrl[0][i].masks);
|
|
|
|
/* global, used by cell_cpu_setup */
|
|
ctr_enabled |= (1 << i);
|
|
}
|
|
}
|
|
|
|
/* initialize the previous counts for the virtual cntrs */
|
|
for_each_online_cpu(cpu)
|
|
for (i = 0; i < num_counters; ++i) {
|
|
per_cpu(pmc_values, cpu)[i] = reset_value[i];
|
|
}
|
|
out:
|
|
;
|
|
}
|
|
|
|
/* This function is called once for each cpu */
|
|
static void cell_cpu_setup(struct op_counter_config *cntr)
|
|
{
|
|
u32 cpu = smp_processor_id();
|
|
u32 num_enabled = 0;
|
|
int i;
|
|
|
|
/* There is one performance monitor per processor chip (i.e. node),
|
|
* so we only need to perform this function once per node.
|
|
*/
|
|
if (cbe_get_hw_thread_id(cpu))
|
|
goto out;
|
|
|
|
if (pm_rtas_token == RTAS_UNKNOWN_SERVICE) {
|
|
printk(KERN_WARNING "%s: RTAS_UNKNOWN_SERVICE\n",
|
|
__FUNCTION__);
|
|
goto out;
|
|
}
|
|
|
|
/* Stop all counters */
|
|
cbe_disable_pm(cpu);
|
|
cbe_disable_pm_interrupts(cpu);
|
|
|
|
cbe_write_pm(cpu, pm_interval, 0);
|
|
cbe_write_pm(cpu, pm_start_stop, 0);
|
|
cbe_write_pm(cpu, group_control, pm_regs.group_control);
|
|
cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
|
|
write_pm_cntrl(cpu);
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
if (ctr_enabled & (1 << i)) {
|
|
pm_signal[num_enabled].cpu = cbe_cpu_to_node(cpu);
|
|
num_enabled++;
|
|
}
|
|
}
|
|
|
|
pm_rtas_activate_signals(cbe_cpu_to_node(cpu), num_enabled);
|
|
out:
|
|
;
|
|
}
|
|
|
|
static void cell_global_start(struct op_counter_config *ctr)
|
|
{
|
|
u32 cpu;
|
|
u32 interrupt_mask = 0;
|
|
u32 i;
|
|
|
|
/* This routine gets called once for the system.
|
|
* There is one performance monitor per node, so we
|
|
* only need to perform this function once per node.
|
|
*/
|
|
for_each_online_cpu(cpu) {
|
|
if (cbe_get_hw_thread_id(cpu))
|
|
continue;
|
|
|
|
interrupt_mask = 0;
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
if (ctr_enabled & (1 << i)) {
|
|
cbe_write_ctr(cpu, i, reset_value[i]);
|
|
enable_ctr(cpu, i, pm_regs.pm07_cntrl);
|
|
interrupt_mask |=
|
|
CBE_PM_CTR_OVERFLOW_INTR(i);
|
|
} else {
|
|
/* Disable counter */
|
|
cbe_write_pm07_control(cpu, i, 0);
|
|
}
|
|
}
|
|
|
|
cbe_get_and_clear_pm_interrupts(cpu);
|
|
cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
|
|
cbe_enable_pm(cpu);
|
|
}
|
|
|
|
virt_cntr_inter_mask = interrupt_mask;
|
|
oprofile_running = 1;
|
|
smp_wmb();
|
|
|
|
/* NOTE: start_virt_cntrs will result in cell_virtual_cntr() being
|
|
* executed which manipulates the PMU. We start the "virtual counter"
|
|
* here so that we do not need to synchronize access to the PMU in
|
|
* the above for-loop.
|
|
*/
|
|
start_virt_cntrs();
|
|
}
|
|
|
|
static void cell_global_stop(void)
|
|
{
|
|
int cpu;
|
|
|
|
/* This routine will be called once for the system.
|
|
* There is one performance monitor per node, so we
|
|
* only need to perform this function once per node.
|
|
*/
|
|
del_timer_sync(&timer_virt_cntr);
|
|
oprofile_running = 0;
|
|
smp_wmb();
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cbe_get_hw_thread_id(cpu))
|
|
continue;
|
|
|
|
cbe_sync_irq(cbe_cpu_to_node(cpu));
|
|
/* Stop the counters */
|
|
cbe_disable_pm(cpu);
|
|
|
|
/* Deactivate the signals */
|
|
pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
|
|
|
|
/* Deactivate interrupts */
|
|
cbe_disable_pm_interrupts(cpu);
|
|
}
|
|
}
|
|
|
|
static void
|
|
cell_handle_interrupt(struct pt_regs *regs, struct op_counter_config *ctr)
|
|
{
|
|
u32 cpu;
|
|
u64 pc;
|
|
int is_kernel;
|
|
unsigned long flags = 0;
|
|
u32 interrupt_mask;
|
|
int i;
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
/* Need to make sure the interrupt handler and the virt counter
|
|
* routine are not running at the same time. See the
|
|
* cell_virtual_cntr() routine for additional comments.
|
|
*/
|
|
spin_lock_irqsave(&virt_cntr_lock, flags);
|
|
|
|
/* Need to disable and reenable the performance counters
|
|
* to get the desired behavior from the hardware. This
|
|
* is hardware specific.
|
|
*/
|
|
|
|
cbe_disable_pm(cpu);
|
|
|
|
interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
|
|
|
|
/* If the interrupt mask has been cleared, then the virt cntr
|
|
* has cleared the interrupt. When the thread that generated
|
|
* the interrupt is restored, the data count will be restored to
|
|
* 0xffffff0 to cause the interrupt to be regenerated.
|
|
*/
|
|
|
|
if ((oprofile_running == 1) && (interrupt_mask != 0)) {
|
|
pc = regs->nip;
|
|
is_kernel = is_kernel_addr(pc);
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(i))
|
|
&& ctr[i].enabled) {
|
|
oprofile_add_pc(pc, is_kernel, i);
|
|
cbe_write_ctr(cpu, i, reset_value[i]);
|
|
}
|
|
}
|
|
|
|
/* The counters were frozen by the interrupt.
|
|
* Reenable the interrupt and restart the counters.
|
|
* If there was a race between the interrupt handler and
|
|
* the virtual counter routine. The virutal counter
|
|
* routine may have cleared the interrupts. Hence must
|
|
* use the virt_cntr_inter_mask to re-enable the interrupts.
|
|
*/
|
|
cbe_enable_pm_interrupts(cpu, hdw_thread,
|
|
virt_cntr_inter_mask);
|
|
|
|
/* The writes to the various performance counters only writes
|
|
* to a latch. The new values (interrupt setting bits, reset
|
|
* counter value etc.) are not copied to the actual registers
|
|
* until the performance monitor is enabled. In order to get
|
|
* this to work as desired, the permormance monitor needs to
|
|
* be disabled while writing to the latches. This is a
|
|
* HW design issue.
|
|
*/
|
|
cbe_enable_pm(cpu);
|
|
}
|
|
spin_unlock_irqrestore(&virt_cntr_lock, flags);
|
|
}
|
|
|
|
struct op_powerpc_model op_model_cell = {
|
|
.reg_setup = cell_reg_setup,
|
|
.cpu_setup = cell_cpu_setup,
|
|
.global_start = cell_global_start,
|
|
.global_stop = cell_global_stop,
|
|
.handle_interrupt = cell_handle_interrupt,
|
|
};
|