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History

Mark Rutland 3cea71bc6b arm64: ensure completion of TLB invalidatation

Currently there is no dsb between the tlbi in __cpu_setup and the write
to SCTLR_EL1 which enables the MMU in __turn_mmu_on. This means that the
TLB invalidation is not guaranteed to have completed at the point
address translation is enabled, leading to a number of possible issues
including incorrect translations and TLB conflict faults.

This patch moves the tlbi in __cpu_setup above an existing dsb used to
synchronise I-cache invalidation, ensuring that the TLBs have been
invalidated at the point the MMU is enabled.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

2013-12-06 17:21:49 +00:00

cache.S

arm64: mm: Fix operands of clz in __flush_dcache_all

2013-05-14 15:44:50 +01:00

context.c

arm64: Process management

2012-09-17 13:41:58 +01:00

copypage.c

arm64: MMU fault handling and page table management

2012-09-17 13:41:57 +01:00

dma-mapping.c

arm64: Call swiotlb_init() instead of swiotlb_init_with_default_size()