mirror of
https://github.com/FEX-Emu/linux.git
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6a01f23033
[Mike Frysinger <vapier.adi@gmail.com>:
- handle bf531/bf532/bf534/bf536 variants in ipipe.h
- cleanup IPIPE logic for bfin_set_irq_handler()
- cleanup ipipe asm code a bit and add missing ENDPROC()
- simplify IPIPE code in trap_c
- unify some of the IPIPE code and fix style
- simplify DO_IRQ_L1 handling with ipipe code
- revert IRQ_SW_INT# addition from ipipe merge
- remove duplicate get_{c,s}clk() prototypes
]
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
225 lines
4.4 KiB
Plaintext
225 lines
4.4 KiB
Plaintext
if (BF561)
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source "arch/blackfin/mach-bf561/boards/Kconfig"
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menu "BF561 Specific Configuration"
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if (!SMP)
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comment "Core B Support"
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config BF561_COREB
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bool "Enable Core B support"
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default y
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config BF561_COREB_RESET
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bool "Enable Core B reset support"
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default n
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help
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This requires code in the application that is loaded
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into Core B. In order to reset, the application needs
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to install an interrupt handler for Supplemental
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Interrupt 0, that sets RETI to 0xff600000 and writes
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bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
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This causes Core B to stall when Supplemental Interrupt
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0 is set, and will reset PC to 0xff600000 when
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COREB_SRAM_INIT is cleared.
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endif
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comment "Interrupt Priority Assignment"
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menu "Priority"
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config IRQ_PLL_WAKEUP
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int "PLL Wakeup Interrupt"
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default 7
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config IRQ_DMA1_ERROR
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int "DMA1 Error (generic)"
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default 7
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config IRQ_DMA2_ERROR
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int "DMA2 Error (generic)"
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default 7
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config IRQ_IMDMA_ERROR
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int "IMDMA Error (generic)"
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default 7
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config IRQ_PPI0_ERROR
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int "PPI0 Error Interrupt"
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default 7
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config IRQ_PPI1_ERROR
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int "PPI1 Error Interrupt"
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default 7
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config IRQ_SPORT0_ERROR
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int "SPORT0 Error Interrupt"
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default 7
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config IRQ_SPORT1_ERROR
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int "SPORT1 Error Interrupt"
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default 7
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config IRQ_SPI_ERROR
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int "SPI Error Interrupt"
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default 7
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config IRQ_UART_ERROR
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int "UART Error Interrupt"
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default 7
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config IRQ_RESERVED_ERROR
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int "Reserved Interrupt"
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default 7
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config IRQ_DMA1_0
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int "DMA1 0 Interrupt(PPI1)"
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default 8
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config IRQ_DMA1_1
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int "DMA1 1 Interrupt(PPI2)"
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default 8
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config IRQ_DMA1_2
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int "DMA1 2 Interrupt"
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default 8
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config IRQ_DMA1_3
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int "DMA1 3 Interrupt"
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default 8
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config IRQ_DMA1_4
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int "DMA1 4 Interrupt"
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default 8
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config IRQ_DMA1_5
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int "DMA1 5 Interrupt"
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default 8
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config IRQ_DMA1_6
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int "DMA1 6 Interrupt"
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default 8
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config IRQ_DMA1_7
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int "DMA1 7 Interrupt"
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default 8
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config IRQ_DMA1_8
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int "DMA1 8 Interrupt"
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default 8
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config IRQ_DMA1_9
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int "DMA1 9 Interrupt"
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default 8
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config IRQ_DMA1_10
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int "DMA1 10 Interrupt"
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default 8
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config IRQ_DMA1_11
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int "DMA1 11 Interrupt"
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default 8
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config IRQ_DMA2_0
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int "DMA2 0 (SPORT0 RX)"
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default 9
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config IRQ_DMA2_1
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int "DMA2 1 (SPORT0 TX)"
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default 9
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config IRQ_DMA2_2
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int "DMA2 2 (SPORT1 RX)"
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default 9
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config IRQ_DMA2_3
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int "DMA2 3 (SPORT2 TX)"
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default 9
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config IRQ_DMA2_4
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int "DMA2 4 (SPI)"
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default 9
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config IRQ_DMA2_5
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int "DMA2 5 (UART RX)"
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default 9
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config IRQ_DMA2_6
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int "DMA2 6 (UART TX)"
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default 9
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config IRQ_DMA2_7
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int "DMA2 7 Interrupt"
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default 9
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config IRQ_DMA2_8
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int "DMA2 8 Interrupt"
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default 9
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config IRQ_DMA2_9
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int "DMA2 9 Interrupt"
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default 9
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config IRQ_DMA2_10
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int "DMA2 10 Interrupt"
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default 9
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config IRQ_DMA2_11
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int "DMA2 11 Interrupt"
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default 9
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config IRQ_TIMER0
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int "TIMER 0 Interrupt"
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default 8
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config IRQ_TIMER1
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int "TIMER 1 Interrupt"
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default 10
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config IRQ_TIMER2
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int "TIMER 2 Interrupt"
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default 10
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config IRQ_TIMER3
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int "TIMER 3 Interrupt"
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default 10
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config IRQ_TIMER4
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int "TIMER 4 Interrupt"
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default 10
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config IRQ_TIMER5
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int "TIMER 5 Interrupt"
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default 10
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config IRQ_TIMER6
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int "TIMER 6 Interrupt"
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default 10
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config IRQ_TIMER7
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int "TIMER 7 Interrupt"
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default 10
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config IRQ_TIMER8
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int "TIMER 8 Interrupt"
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default 10
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config IRQ_TIMER9
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int "TIMER 9 Interrupt"
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default 10
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config IRQ_TIMER10
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int "TIMER 10 Interrupt"
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default 10
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config IRQ_TIMER11
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int "TIMER 11 Interrupt"
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default 10
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config IRQ_PROG0_INTA
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int "Programmable Flags0 A (8)"
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default 11
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config IRQ_PROG0_INTB
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int "Programmable Flags0 B (8)"
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default 11
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config IRQ_PROG1_INTA
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int "Programmable Flags1 A (8)"
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default 11
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config IRQ_PROG1_INTB
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int "Programmable Flags1 B (8)"
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default 11
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config IRQ_PROG2_INTA
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int "Programmable Flags2 A (8)"
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default 11
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config IRQ_PROG2_INTB
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int "Programmable Flags2 B (8)"
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default 11
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config IRQ_DMA1_WRRD0
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int "MDMA1 0 write/read INT"
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default 8
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config IRQ_DMA1_WRRD1
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int "MDMA1 1 write/read INT"
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default 8
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config IRQ_DMA2_WRRD0
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int "MDMA2 0 write/read INT"
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default 9
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config IRQ_DMA2_WRRD1
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int "MDMA2 1 write/read INT"
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default 9
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config IRQ_IMDMA_WRRD0
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int "IMDMA 0 write/read INT"
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default 12
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config IRQ_IMDMA_WRRD1
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int "IMDMA 1 write/read INT"
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default 12
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config IRQ_WDTIMER
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int "Watch Dog Timer"
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default 13
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help
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Enter the priority numbers between 7-13 ONLY. Others are Reserved.
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This applies to all the above. It is not recommended to assign the
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highest priority number 7 to UART or any other device.
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endmenu
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endmenu
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endif
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