Paul Walmsley 1c472d8e82 clk: tegra: T114: add DFLL DVCO reset control ... Add DFLL DVCO reset line control functions to the CAR IP block driver. The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-06-18 11:28:51 -07:00
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clk-audio-sync.c
clk-divider.c
clk-periph-gate.c	clk: tegra: Workaround for Tegra114 MSENC problem	2013-04-04 16:10:59 -06:00
clk-periph.c	clk: tegra: Add flags to tegra_clk_periph()	2013-04-04 16:10:56 -06:00
clk-pll-out.c
clk-pll.c	clk: tegra: Use override bits when needed	2013-06-11 18:00:32 -07:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: Use common of_clk_init function	2013-05-31 12:57:25 -07:00
clk-tegra30.c	clk: tegra: override bits for Tegra30 PLLM	2013-06-11 18:00:23 -07:00
clk-tegra114.c	clk: tegra: T114: add DFLL DVCO reset control	2013-06-18 11:28:51 -07:00
clk.c	clk: tegra: Use common of_clk_init function	2013-05-31 12:57:25 -07:00
clk.h	clk: tegra: T114: add DFLL DVCO reset control	2013-06-18 11:28:51 -07:00
Makefile	clk: tegra: Implement clocks for Tegra114	2013-04-04 17:17:12 -06:00