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4fb2847437
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.
Now we have three prefetch abort model:
* legacy - for CPUs before ARMv6. They doesn't provide neither
IFSR nor IFAR. We simulate IFSR with section translation fault
status for them to generalize code;
* ARMv6 - provides IFSR, but not IFAR;
* ARMv7 - provides both IFSR and IFAR.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
20 lines
389 B
ArmAsm
20 lines
389 B
ArmAsm
#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Function: legacy_pabort
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*
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* Params : r0 = address of aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = Simulated IFSR with section translation fault status
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*
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* Purpose : obtain information about current prefetch abort.
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*/
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.align 5
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ENTRY(legacy_pabort)
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mov r1, #5
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mov pc, lr
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ENDPROC(legacy_pabort)
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