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200b812d00
The patch adds a CLREX or dummy STREX to the exception return path. This is needed because several atomic/locking operations use a pair of LDREX/STREXEQ and the EQ condition may not always be satisfied. This would leave the exclusive monitor status set and may cause problems with atomic/locking operations in the interrupted code. With this patch, the atomic_set() operation can be a simple STR instruction (on SMP systems, the global exclusive monitor is cleared by STR anyway). Clearing the exclusive monitor during context switch is no longer needed as this is handled by the exception return path anyway. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Jamie Lokier <jamie@shareable.org>
163 lines
4.2 KiB
ArmAsm
163 lines
4.2 KiB
ArmAsm
#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/thread_info.h>
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@ Bad Abort numbers
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@ -----------------
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@
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#define BAD_PREFETCH 0
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#define BAD_DATA 1
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#define BAD_ADDREXCPTN 2
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#define BAD_IRQ 3
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#define BAD_UNDEFINSTR 4
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@
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@ Most of the stack format comes from struct pt_regs, but with
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@ the addition of 8 bytes for storing syscall args 5 and 6.
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@ This _must_ remain a multiple of 8 for EABI.
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@
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#define S_OFF 8
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/*
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* The SWI code relies on the fact that R0 is at the bottom of the stack
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* (due to slow/fast restore user regs).
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*/
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#if S_R0 != 0
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#error "Please fix"
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#endif
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.macro zero_fp
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#ifdef CONFIG_FRAME_POINTER
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mov fp, #0
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#endif
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.endm
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.macro alignment_trap, rtemp
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#ifdef CONFIG_ALIGNMENT_TRAP
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ldr \rtemp, .LCcralign
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ldr \rtemp, [\rtemp]
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mcr p15, 0, \rtemp, c1, c0
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#endif
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.endm
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@
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@ Store/load the USER SP and LR registers by switching to the SYS
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@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
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@ available. Should only be called from SVC mode
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@
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.macro store_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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str sp, [\rd, #\offset] @ save sp_usr
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str lr, [\rd, #\offset + 4] @ save lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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.macro load_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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ldr sp, [\rd, #\offset] @ load sp_usr
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ldr lr, [\rd, #\offset + 4] @ load lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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#ifndef CONFIG_THUMB2_KERNEL
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.macro svc_exit, rpsr
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msr spsr_cxsf, \rpsr
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#if defined(CONFIG_CPU_32v6K)
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clrex @ clear the exclusive monitor
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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#elif defined (CONFIG_CPU_V6)
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ldr r0, [sp]
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strex r1, r2, [sp] @ clear the exclusive monitor
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ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr
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#endif
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.endm
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.macro restore_user_regs, fast = 0, offset = 0
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ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
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ldr lr, [sp, #\offset + S_PC]! @ get pc
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msr spsr_cxsf, r1 @ save in spsr_svc
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#if defined(CONFIG_CPU_32v6K)
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clrex @ clear the exclusive monitor
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#elif defined (CONFIG_CPU_V6)
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strex r1, r2, [sp] @ clear the exclusive monitor
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#endif
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.if \fast
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ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
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.else
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ldmdb sp, {r0 - lr}^ @ get calling r0 - lr
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.endif
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add sp, sp, #S_FRAME_SIZE - S_PC
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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.macro get_thread_info, rd
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mov \rd, sp, lsr #13
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mov \rd, \rd, lsl #13
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.endm
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#else /* CONFIG_THUMB2_KERNEL */
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.macro svc_exit, rpsr
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clrex @ clear the exclusive monitor
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ldr r0, [sp, #S_SP] @ top of the stack
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ldr r1, [sp, #S_PC] @ return address
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tst r0, #4 @ orig stack 8-byte aligned?
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stmdb r0, {r1, \rpsr} @ rfe context
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ldmia sp, {r0 - r12}
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ldr lr, [sp, #S_LR]
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addeq sp, sp, #S_FRAME_SIZE - 8 @ aligned
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addne sp, sp, #S_FRAME_SIZE - 4 @ not aligned
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rfeia sp!
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.endm
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.macro restore_user_regs, fast = 0, offset = 0
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clrex @ clear the exclusive monitor
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mov r2, sp
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load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
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ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
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ldr lr, [sp, #\offset + S_PC] @ get pc
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add sp, sp, #\offset + S_SP
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msr spsr_cxsf, r1 @ save in spsr_svc
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.if \fast
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ldmdb sp, {r1 - r12} @ get calling r1 - r12
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.else
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ldmdb sp, {r0 - r12} @ get calling r0 - r12
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.endif
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add sp, sp, #S_FRAME_SIZE - S_SP
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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.macro get_thread_info, rd
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mov \rd, sp
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lsr \rd, \rd, #13
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mov \rd, \rd, lsl #13
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.endm
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#endif /* !CONFIG_THUMB2_KERNEL */
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - r0 to r6.
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*
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* r7 is reserved for the system call number for thumb mode.
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*
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* Note that tbl == why is intentional.
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*
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* We must set at least "tsk" and "why" when calling ret_with_reschedule.
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*/
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scno .req r7 @ syscall number
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tbl .req r8 @ syscall table pointer
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why .req r8 @ Linux syscall (!= 0)
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tsk .req r9 @ current thread_info
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