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On AT91 processors that include an ECC controller, pass its base address to the NAND driver via platform_device resources. Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
/*
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* include/asm-arm/arch-at91/at91_ecc.h
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*
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* Error Corrected Code Controller (ECC) - System peripherals regsters.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef AT91_ECC_H
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#define AT91_ECC_H
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#define AT91_ECC_CR 0x00 /* Control register */
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#define AT91_ECC_RST (1 << 0) /* Reset parity */
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#define AT91_ECC_MR 0x04 /* Mode register */
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#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
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#define AT91_ECC_PAGESIZE_528 (0)
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#define AT91_ECC_PAGESIZE_1056 (1)
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#define AT91_ECC_PAGESIZE_2112 (2)
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#define AT91_ECC_PAGESIZE_4224 (3)
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#define AT91_ECC_SR 0x08 /* Status register */
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#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
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#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
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#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
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#define AT91_ECC_PR 0x0c /* Parity register */
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#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
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#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
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#define AT91_ECC_NPR 0x10 /* NParity register */
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#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
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#endif
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