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38c677cb9a
Patch from David Brownell
ARM genirq cleanups/updates:
- Start switching platforms to newer APIs
* use "irq_chip" name, not "irqchip"
* providing irq_chip.name
- Show irq_chip.name in /proc/interrupts, like on x86.
This update a bit more than half of the ARM code. The irq_chip.name
values were chosen to match docs (if I have them) or be otherwise
obvious ("FPGA", "CPLD", or matching the code).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
98 lines
2.2 KiB
C
98 lines
2.2 KiB
C
/*
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* linux/arch/arm/mach-iop3xx/iop321-irq.c
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*
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* Generic IOP321 IRQ handling functionality
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Added IOP3XX chipset and IQ80321 board masking code.
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*
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static u32 iop321_mask /* = 0 */;
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static inline void intctl_write(u32 val)
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{
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asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
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}
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static inline void intstr_write(u32 val)
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{
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asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
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}
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static void
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iop321_irq_mask (unsigned int irq)
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{
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iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS));
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intctl_write(iop321_mask);
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}
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static void
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iop321_irq_unmask (unsigned int irq)
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{
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iop321_mask |= (1 << (irq - IOP321_IRQ_OFS));
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intctl_write(iop321_mask);
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}
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struct irq_chip ext_chip = {
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.name = "IOP",
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.ack = iop321_irq_mask,
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.mask = iop321_irq_mask,
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.unmask = iop321_irq_unmask,
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};
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void __init iop321_init_irq(void)
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{
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unsigned int i, tmp;
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/* Enable access to coprocessor 6 for dealing with IRQs.
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* From RMK:
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* Basically, the Intel documentation here is poor. It appears that
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* you need to set the bit to be able to access the coprocessor from
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* SVC mode. Whether that allows access from user space or not is
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* unclear.
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*/
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, %1\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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/* The action is delayed, so we have to do this: */
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4"
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: "=r" (tmp) : "i" (1 << 6) );
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intctl_write(0); // disable all interrupts
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intstr_write(0); // treat all as IRQ
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if(machine_is_iq80321() ||
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machine_is_iq31244()) // all interrupts are inputs to chip
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*IOP321_PCIIRSR = 0x0f;
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for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++)
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{
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set_irq_chip(i, &ext_chip);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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