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9c857a8e89
The security accelerator within MCU domain supports two ports similarly to the SA2UL in MAIN domain. Add endpoint configuration for the two ingress and one egress threads of the second port. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20200803100724.19003-1-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
226 lines
5.3 KiB
C
226 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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#define PSIL_SA2UL(x, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.notdpkt = tx, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep j721e_src_ep_map[] = {
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/* SA2UL */
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PSIL_SA2UL(0x4000, 0),
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PSIL_SA2UL(0x4001, 0),
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PSIL_SA2UL(0x4002, 0),
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PSIL_SA2UL(0x4003, 0),
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0x4100),
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PSIL_ETHERNET(0x4101),
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PSIL_ETHERNET(0x4102),
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PSIL_ETHERNET(0x4103),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0x4200),
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PSIL_ETHERNET(0x4201),
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PSIL_ETHERNET(0x4202),
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PSIL_ETHERNET(0x4203),
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/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
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PSIL_PDMA_MCASP(0x4400),
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PSIL_PDMA_MCASP(0x4401),
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PSIL_PDMA_MCASP(0x4402),
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/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
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PSIL_PDMA_MCASP(0x4500),
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PSIL_PDMA_MCASP(0x4501),
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PSIL_PDMA_MCASP(0x4502),
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PSIL_PDMA_MCASP(0x4503),
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PSIL_PDMA_MCASP(0x4504),
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PSIL_PDMA_MCASP(0x4505),
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PSIL_PDMA_MCASP(0x4506),
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PSIL_PDMA_MCASP(0x4507),
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PSIL_PDMA_MCASP(0x4508),
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/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
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PSIL_PDMA_XY_PKT(0x4600),
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PSIL_PDMA_XY_PKT(0x4601),
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PSIL_PDMA_XY_PKT(0x4602),
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PSIL_PDMA_XY_PKT(0x4603),
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PSIL_PDMA_XY_PKT(0x4604),
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PSIL_PDMA_XY_PKT(0x4605),
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PSIL_PDMA_XY_PKT(0x4606),
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PSIL_PDMA_XY_PKT(0x4607),
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/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
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PSIL_PDMA_XY_PKT(0x460c),
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PSIL_PDMA_XY_PKT(0x460d),
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PSIL_PDMA_XY_PKT(0x460e),
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PSIL_PDMA_XY_PKT(0x460f),
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PSIL_PDMA_XY_PKT(0x4610),
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PSIL_PDMA_XY_PKT(0x4611),
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PSIL_PDMA_XY_PKT(0x4612),
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PSIL_PDMA_XY_PKT(0x4613),
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/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
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PSIL_PDMA_XY_PKT(0x4618),
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PSIL_PDMA_XY_PKT(0x4619),
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PSIL_PDMA_XY_PKT(0x461a),
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PSIL_PDMA_XY_PKT(0x461b),
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PSIL_PDMA_XY_PKT(0x461c),
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PSIL_PDMA_XY_PKT(0x461d),
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PSIL_PDMA_XY_PKT(0x461e),
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PSIL_PDMA_XY_PKT(0x461f),
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/* PDMA11 (PDMA_MISC_G3) */
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PSIL_PDMA_XY_PKT(0x4624),
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PSIL_PDMA_XY_PKT(0x4625),
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PSIL_PDMA_XY_PKT(0x4626),
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PSIL_PDMA_XY_PKT(0x4627),
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PSIL_PDMA_XY_PKT(0x4628),
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PSIL_PDMA_XY_PKT(0x4629),
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PSIL_PDMA_XY_PKT(0x4630),
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PSIL_PDMA_XY_PKT(0x463a),
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/* PDMA13 (PDMA_USART_G0) - UART0-1 */
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PSIL_PDMA_XY_PKT(0x4700),
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PSIL_PDMA_XY_PKT(0x4701),
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/* PDMA14 (PDMA_USART_G1) - UART2-3 */
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PSIL_PDMA_XY_PKT(0x4702),
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PSIL_PDMA_XY_PKT(0x4703),
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/* PDMA15 (PDMA_USART_G2) - UART4-9 */
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PSIL_PDMA_XY_PKT(0x4704),
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PSIL_PDMA_XY_PKT(0x4705),
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PSIL_PDMA_XY_PKT(0x4706),
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PSIL_PDMA_XY_PKT(0x4707),
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PSIL_PDMA_XY_PKT(0x4708),
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PSIL_PDMA_XY_PKT(0x4709),
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/* CPSW9 */
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PSIL_ETHERNET(0x4a00),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
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PSIL_PDMA_XY_PKT(0x7100),
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PSIL_PDMA_XY_PKT(0x7101),
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PSIL_PDMA_XY_PKT(0x7102),
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PSIL_PDMA_XY_PKT(0x7103),
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/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
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PSIL_PDMA_XY_PKT(0x7200),
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PSIL_PDMA_XY_PKT(0x7201),
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PSIL_PDMA_XY_PKT(0x7202),
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PSIL_PDMA_XY_PKT(0x7203),
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PSIL_PDMA_XY_PKT(0x7204),
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PSIL_PDMA_XY_PKT(0x7205),
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PSIL_PDMA_XY_PKT(0x7206),
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PSIL_PDMA_XY_PKT(0x7207),
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/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
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PSIL_PDMA_XY_PKT(0x7300),
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/* MCU_PDMA_ADC - ADC0-1 */
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PSIL_PDMA_XY_TR(0x7400),
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PSIL_PDMA_XY_TR(0x7401),
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PSIL_PDMA_XY_TR(0x7402),
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PSIL_PDMA_XY_TR(0x7403),
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep j721e_dst_ep_map[] = {
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/* SA2UL */
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PSIL_SA2UL(0xc000, 1),
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PSIL_SA2UL(0xc001, 1),
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0xc100),
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PSIL_ETHERNET(0xc101),
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PSIL_ETHERNET(0xc102),
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PSIL_ETHERNET(0xc103),
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PSIL_ETHERNET(0xc104),
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PSIL_ETHERNET(0xc105),
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PSIL_ETHERNET(0xc106),
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PSIL_ETHERNET(0xc107),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0xc200),
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PSIL_ETHERNET(0xc201),
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PSIL_ETHERNET(0xc202),
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PSIL_ETHERNET(0xc203),
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PSIL_ETHERNET(0xc204),
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PSIL_ETHERNET(0xc205),
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PSIL_ETHERNET(0xc206),
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PSIL_ETHERNET(0xc207),
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/* CPSW9 */
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PSIL_ETHERNET(0xca00),
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PSIL_ETHERNET(0xca01),
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PSIL_ETHERNET(0xca02),
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PSIL_ETHERNET(0xca03),
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PSIL_ETHERNET(0xca04),
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PSIL_ETHERNET(0xca05),
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PSIL_ETHERNET(0xca06),
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PSIL_ETHERNET(0xca07),
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/* CPSW0 */
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PSIL_ETHERNET(0xf000),
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PSIL_ETHERNET(0xf001),
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PSIL_ETHERNET(0xf002),
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PSIL_ETHERNET(0xf003),
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PSIL_ETHERNET(0xf004),
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),
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};
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struct psil_ep_map j721e_ep_map = {
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.name = "j721e",
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.src = j721e_src_ep_map,
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.src_count = ARRAY_SIZE(j721e_src_ep_map),
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.dst = j721e_dst_ep_map,
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.dst_count = ARRAY_SIZE(j721e_dst_ep_map),
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};
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