Alexander Duyck 4352aa5bbf PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset ... While testing completion timeouts I found that hardware was not recovering. It looks like the hot reset was never being propagated to the endpoint devices on the bus due to the fact that we were clearing the bit too quickly. The documentation I have states that we should be transmitting hot reset TS1s for 2ms. To achieve this I have added a 2ms delay from the time we set the secondary bus reset bit to the time we clear it. In addition I changed the define used for the secondary bus reset bit to match the register define that was being used. Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>		2010-04-08 09:24:11 -07:00
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aer	PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset	2010-04-08 09:24:11 -07:00
pme	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
aspm.c
Kconfig
Makefile
portdrv_bus.c
portdrv_core.c
portdrv_pci.c	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
portdrv.h