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2e2446ea07
Comments in head.S suggest that the iSeries naca has a fixed address, because tools expect to find it there. The only tool which appears to access the naca is addRamDisk, but both the in-kernel version and the version used in RHEL and SuSE in fact locate the NACA the same way as the hypervisor does, by following the pointer in the hvReleaseData structure. Since the requirement for a fixed address seems to be obsolete, this patch removes the naca from head.S and replaces it with a normal C initializer. For good measure, it removes an old version of addRamDisk.c which was sitting, unused, in the ppc32 tree. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
254 lines
9.0 KiB
C
254 lines
9.0 KiB
C
/*
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* Copyright 2001 Mike Corrigan, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/naca.h>
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#include <asm/abs_addr.h>
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#include <asm/iSeries/ItLpNaca.h>
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#include <asm/lppaca.h>
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#include <asm/iSeries/ItLpRegSave.h>
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#include <asm/paca.h>
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#include <asm/iSeries/HvReleaseData.h>
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#include <asm/iSeries/LparMap.h>
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#include <asm/iSeries/ItVpdAreas.h>
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#include <asm/iSeries/ItIplParmsReal.h>
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#include <asm/iSeries/ItExtVpdPanel.h>
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#include <asm/iSeries/ItLpQueue.h>
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#include <asm/iSeries/IoHriProcessorVpd.h>
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#include <asm/iSeries/ItSpCommArea.h>
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/* The HvReleaseData is the root of the information shared between
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* the hypervisor and Linux.
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*/
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struct HvReleaseData hvReleaseData = {
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.xDesc = 0xc8a5d9c4, /* "HvRD" ebcdic */
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.xSize = sizeof(struct HvReleaseData),
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.xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
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.xSlicNacaAddr = &naca, /* 64-bit Naca address */
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.xMsNucDataOffset = LPARMAP_PHYS,
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.xFlags = HVREL_TAGSINACTIVE /* tags inactive */
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/* 64 bit */
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/* shared processors */
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/* HMT allowed */
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| 6, /* TEMP: This allows non-GA driver */
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.xVrmIndex = 4, /* We are v5r2m0 */
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.xMinSupportedPlicVrmIndex = 3, /* v5r1m0 */
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.xMinCompatablePlicVrmIndex = 3, /* v5r1m0 */
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.xVrmName = { 0xd3, 0x89, 0x95, 0xa4, /* "Linux 2.4.64" ebcdic */
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0xa7, 0x40, 0xf2, 0x4b,
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0xf4, 0x4b, 0xf6, 0xf4 },
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};
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/*
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* The NACA. The first dword of the naca is required by the iSeries
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* hypervisor to point to itVpdAreas. The hypervisor finds the NACA
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* through the pointer in hvReleaseData.
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*/
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struct naca_struct naca = {
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.xItVpdAreas = &itVpdAreas,
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.xRamDisk = 0,
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.xRamDiskSize = 0,
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};
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extern void system_reset_iSeries(void);
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extern void machine_check_iSeries(void);
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extern void data_access_iSeries(void);
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extern void instruction_access_iSeries(void);
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extern void hardware_interrupt_iSeries(void);
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extern void alignment_iSeries(void);
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extern void program_check_iSeries(void);
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extern void fp_unavailable_iSeries(void);
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extern void decrementer_iSeries(void);
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extern void trap_0a_iSeries(void);
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extern void trap_0b_iSeries(void);
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extern void system_call_iSeries(void);
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extern void single_step_iSeries(void);
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extern void trap_0e_iSeries(void);
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extern void performance_monitor_iSeries(void);
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extern void data_access_slb_iSeries(void);
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extern void instruction_access_slb_iSeries(void);
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struct ItLpNaca itLpNaca = {
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.xDesc = 0xd397d581, /* "LpNa" ebcdic */
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.xSize = 0x0400, /* size of ItLpNaca */
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.xIntHdlrOffset = 0x0300, /* offset to int array */
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.xMaxIntHdlrEntries = 19, /* # ents */
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.xPrimaryLpIndex = 0, /* Part # of primary */
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.xServiceLpIndex = 0, /* Part # of serv */
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.xLpIndex = 0, /* Part # of me */
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.xMaxLpQueues = 0, /* # of LP queues */
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.xLpQueueOffset = 0x100, /* offset of start of LP queues */
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.xPirEnvironMode = 0, /* Piranha stuff */
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.xPirConsoleMode = 0,
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.xPirDasdMode = 0,
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.xLparInstalled = 0,
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.xSysPartitioned = 0,
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.xHwSyncedTBs = 0,
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.xIntProcUtilHmt = 0,
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.xSpVpdFormat = 0,
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.xIntProcRatio = 0,
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.xPlicVrmIndex = 0, /* VRM index of PLIC */
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.xMinSupportedSlicVrmInd = 0, /* min supported SLIC */
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.xMinCompatableSlicVrmInd = 0, /* min compat SLIC */
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.xLoadAreaAddr = 0, /* 64-bit addr of load area */
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.xLoadAreaChunks = 0, /* chunks for load area */
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.xPaseSysCallCRMask = 0, /* PASE mask */
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.xSlicSegmentTablePtr = 0, /* seg table */
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.xOldLpQueue = { 0 }, /* Old LP Queue */
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.xInterruptHdlr = {
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(u64)system_reset_iSeries, /* 0x100 System Reset */
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(u64)machine_check_iSeries, /* 0x200 Machine Check */
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(u64)data_access_iSeries, /* 0x300 Data Access */
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(u64)instruction_access_iSeries, /* 0x400 Instruction Access */
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(u64)hardware_interrupt_iSeries, /* 0x500 External */
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(u64)alignment_iSeries, /* 0x600 Alignment */
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(u64)program_check_iSeries, /* 0x700 Program Check */
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(u64)fp_unavailable_iSeries, /* 0x800 FP Unavailable */
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(u64)decrementer_iSeries, /* 0x900 Decrementer */
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(u64)trap_0a_iSeries, /* 0xa00 Trap 0A */
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(u64)trap_0b_iSeries, /* 0xb00 Trap 0B */
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(u64)system_call_iSeries, /* 0xc00 System Call */
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(u64)single_step_iSeries, /* 0xd00 Single Step */
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(u64)trap_0e_iSeries, /* 0xe00 Trap 0E */
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(u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
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0, /* int 0x1000 */
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0, /* int 0x1010 */
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0, /* int 0x1020 CPU ctls */
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(u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
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(u64)data_access_slb_iSeries, /* 0x380 D-SLB */
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(u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
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}
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};
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EXPORT_SYMBOL(itLpNaca);
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
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EXPORT_SYMBOL(xItExtVpdPanel);
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#define maxPhysicalProcessors 32
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struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
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{
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.xInstCacheOperandSize = 32,
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.xDataCacheOperandSize = 32,
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.xProcFreq = 50000000,
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.xTimeBaseFreq = 50000000,
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.xPVR = 0x3600
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}
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};
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/* Space for Main Store Vpd 27,200 bytes */
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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u64 xMsVpd[3400] __attribute__((__section__(".data")));
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/* Space for Recovery Log Buffer */
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/* May be filled in by the hypervisor so cannot end up in the BSS */
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u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
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struct SpCommArea xSpCommArea = {
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.xDesc = 0xE2D7C3C2,
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.xFormat = 1,
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};
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/* The LparMap data is now located at offset 0x6000 in head.S
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* It was put there so that the HvReleaseData could address it
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* with a 32-bit offset as required by the iSeries hypervisor
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*
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* The Naca has a pointer to the ItVpdAreas. The hypervisor finds
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* the Naca via the HvReleaseData area. The HvReleaseData has the
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* offset into the Naca of the pointer to the ItVpdAreas.
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*/
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struct ItVpdAreas itVpdAreas = {
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.xSlicDesc = 0xc9a3e5c1, /* "ItVA" */
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.xSlicSize = sizeof(struct ItVpdAreas),
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.xSlicVpdEntries = ItVpdMaxEntries, /* # VPD array entries */
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.xSlicDmaEntries = ItDmaMaxEntries, /* # DMA array entries */
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.xSlicMaxLogicalProcs = NR_CPUS * 2, /* Max logical procs */
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.xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
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.xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
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.xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
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.xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
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.xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
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.xSlicMaxSlotLabels = 0, /* max slot labels */
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.xSlicMaxLpQueues = 1, /* max LP queues */
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.xPlicDmaLens = { 0 }, /* DMA lengths */
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.xPlicDmaToks = { 0 }, /* DMA tokens */
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.xSlicVpdLens = { /* VPD lengths */
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0,0,0, /* 0 - 2 */
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sizeof(xItExtVpdPanel), /* 3 Extended VPD */
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sizeof(struct paca_struct), /* 4 length of Paca */
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0, /* 5 */
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sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
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26992, /* 7 length of MS VPD */
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0, /* 8 */
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sizeof(struct ItLpNaca),/* 9 length of LP Naca */
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0, /* 10 */
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256, /* 11 length of Recovery Log Buf */
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sizeof(struct SpCommArea), /* 12 length of SP Comm Area */
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0,0,0, /* 13 - 15 */
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sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
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0,0,0,0,0,0, /* 17 - 22 */
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sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
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0,0 /* 24 - 25 */
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},
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.xSlicVpdAdrs = { /* VPD addresses */
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0,0,0, /* 0 - 2 */
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&xItExtVpdPanel, /* 3 Extended VPD */
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&paca[0], /* 4 first Paca */
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0, /* 5 */
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&xItIplParmsReal, /* 6 IPL parms */
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&xMsVpd, /* 7 MS Vpd */
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0, /* 8 */
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&itLpNaca, /* 9 LpNaca */
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0, /* 10 */
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&xRecoveryLogBuffer, /* 11 Recovery Log Buffer */
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&xSpCommArea, /* 12 SP Comm Area */
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0,0,0, /* 13 - 15 */
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&xIoHriProcessorVpd, /* 16 Proc Vpd */
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0,0,0,0,0,0, /* 17 - 22 */
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&hvlpevent_queue, /* 23 Lp Queue */
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0,0
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}
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};
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struct msChunks msChunks;
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EXPORT_SYMBOL(msChunks);
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/* Depending on whether this is called from iSeries or pSeries setup
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* code, the location of the msChunks struct may or may not have
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* to be reloc'd, so we force the caller to do that for us by passing
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* in a pointer to the structure.
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*/
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unsigned long
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msChunks_alloc(unsigned long mem, unsigned long num_chunks, unsigned long chunk_size)
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{
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unsigned long offset = reloc_offset();
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struct msChunks *_msChunks = PTRRELOC(&msChunks);
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_msChunks->num_chunks = num_chunks;
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_msChunks->chunk_size = chunk_size;
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_msChunks->chunk_shift = __ilog2(chunk_size);
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_msChunks->chunk_mask = (1UL<<_msChunks->chunk_shift)-1;
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mem = _ALIGN(mem, sizeof(msChunks_entry));
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_msChunks->abs = (msChunks_entry *)(mem + offset);
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mem += num_chunks * sizeof(msChunks_entry);
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return mem;
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}
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