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9370b35175
Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs. Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
155 lines
3.2 KiB
ArmAsm
155 lines
3.2 KiB
ArmAsm
/*
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* Copyright 2002 Embedded Edge, LLC
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* Author: dan@embeddededge.com
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*
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* Sleep helper for Au1xxx sleep mode.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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.text
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.set macro
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.set noat
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.align 5
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/* Save all of the processor general registers and go to sleep.
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* A wakeup condition will get us back here to restore the registers.
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*/
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LEAF(save_and_sleep)
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subu sp, PT_SIZE
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sw $1, PT_R1(sp)
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sw $2, PT_R2(sp)
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sw $3, PT_R3(sp)
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sw $4, PT_R4(sp)
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sw $5, PT_R5(sp)
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sw $6, PT_R6(sp)
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sw $7, PT_R7(sp)
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sw $8, PT_R8(sp)
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sw $9, PT_R9(sp)
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sw $10, PT_R10(sp)
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sw $11, PT_R11(sp)
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sw $12, PT_R12(sp)
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sw $13, PT_R13(sp)
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sw $14, PT_R14(sp)
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sw $15, PT_R15(sp)
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sw $16, PT_R16(sp)
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sw $17, PT_R17(sp)
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sw $18, PT_R18(sp)
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sw $19, PT_R19(sp)
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sw $20, PT_R20(sp)
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sw $21, PT_R21(sp)
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sw $22, PT_R22(sp)
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sw $23, PT_R23(sp)
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sw $24, PT_R24(sp)
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sw $25, PT_R25(sp)
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sw $26, PT_R26(sp)
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sw $27, PT_R27(sp)
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sw $28, PT_R28(sp)
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sw $29, PT_R29(sp)
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sw $30, PT_R30(sp)
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sw $31, PT_R31(sp)
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mfc0 k0, CP0_STATUS
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sw k0, 0x20(sp)
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mfc0 k0, CP0_CONTEXT
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sw k0, 0x1c(sp)
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mfc0 k0, CP0_PAGEMASK
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sw k0, 0x18(sp)
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mfc0 k0, CP0_CONFIG
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sw k0, 0x14(sp)
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/* Now set up the scratch registers so the boot rom will
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* return to this point upon wakeup.
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*/
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la k0, 1f
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lui k1, 0xb190
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ori k1, 0x18
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sw sp, 0(k1)
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ori k1, 0x1c
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sw k0, 0(k1)
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/* Put SDRAM into self refresh. Preload instructions into cache,
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* issue a precharge, then auto refresh, then sleep commands to it.
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*/
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la t0, sdsleep
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.set mips3
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cache 0x14, 0(t0)
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cache 0x14, 32(t0)
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cache 0x14, 64(t0)
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cache 0x14, 96(t0)
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.set mips0
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sdsleep:
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lui k0, 0xb400
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sw zero, 0x001c(k0) /* Precharge */
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sw zero, 0x0020(k0) /* Auto refresh */
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sw zero, 0x0030(k0) /* SDRAM sleep */
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sync
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lui k1, 0xb190
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sw zero, 0x0078(k1) /* get ready to sleep */
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sync
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sw zero, 0x007c(k1) /* Put processor to sleep */
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sync
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/* This is where we return upon wakeup.
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* Reload all of the registers and return.
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*/
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1: nop
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lw k0, 0x20(sp)
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mtc0 k0, CP0_STATUS
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lw k0, 0x1c(sp)
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mtc0 k0, CP0_CONTEXT
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lw k0, 0x18(sp)
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mtc0 k0, CP0_PAGEMASK
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lw k0, 0x14(sp)
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mtc0 k0, CP0_CONFIG
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/* We need to catch the ealry Alchemy SOCs with
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* the write-only Config[OD] bit and set it back to one...
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*/
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jal au1x00_fixup_config_od
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lw $1, PT_R1(sp)
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lw $2, PT_R2(sp)
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lw $3, PT_R3(sp)
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lw $4, PT_R4(sp)
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lw $5, PT_R5(sp)
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lw $6, PT_R6(sp)
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lw $7, PT_R7(sp)
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lw $8, PT_R8(sp)
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lw $9, PT_R9(sp)
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lw $10, PT_R10(sp)
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lw $11, PT_R11(sp)
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lw $12, PT_R12(sp)
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lw $13, PT_R13(sp)
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lw $14, PT_R14(sp)
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lw $15, PT_R15(sp)
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lw $16, PT_R16(sp)
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lw $17, PT_R17(sp)
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lw $18, PT_R18(sp)
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lw $19, PT_R19(sp)
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lw $20, PT_R20(sp)
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lw $21, PT_R21(sp)
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lw $22, PT_R22(sp)
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lw $23, PT_R23(sp)
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lw $24, PT_R24(sp)
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lw $25, PT_R25(sp)
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lw $26, PT_R26(sp)
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lw $27, PT_R27(sp)
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lw $28, PT_R28(sp)
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lw $29, PT_R29(sp)
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lw $30, PT_R30(sp)
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lw $31, PT_R31(sp)
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addiu sp, PT_SIZE
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jr ra
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END(save_and_sleep)
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