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4f84e4be53
Background:
When a userspace application wants to know about machine check events, it
opens /dev/mcelog and does a read(). Usually, we found that this interface
works well, but in some cases, when the system was taking large numbers of
machine check exceptions, the read() would hang. The system would output a
soft-lockup warning, and the daemon reading from /dev/mcelog would suck up
as much of a single CPU as it could spinning in system space.
Description:
This patch fixes this bug. In particular, there was a "continue" inside a
timeout loop that presumably was intended to break out of the outer loop,
but instead caused the inner loop to continue. This patch also makes the
condition for the break-out a little more evident by changing a
!time_before to a time_after_eq.
Result:
The read() no longer hangs in this test case.
Testing:
On my system, I could replicate the bug with the following command:
# for i in `seq 15000`; do ./inject_sbe.sh; done
where inject_sbe.sh contains commands to inject a single-bit error into the
next memory write transaction.
Patch:
This patch is against git f1518a088b
.
Signed-off-by: Joshua Wise <jwise@google.com>
Signed-off-by: Tim Hockin <thockin@google.com>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
759 lines
18 KiB
C
759 lines
18 KiB
C
/*
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* Machine check handler.
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* K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
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* Rest from unknown author(s).
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* 2004 Andi Kleen. Rewrote most of it.
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/rcupdate.h>
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#include <linux/kallsyms.h>
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#include <linux/sysdev.h>
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#include <linux/miscdevice.h>
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#include <linux/fs.h>
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#include <linux/capability.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/ctype.h>
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#include <linux/kmod.h>
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#include <linux/kdebug.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/mce.h>
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#include <asm/uaccess.h>
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#include <asm/smp.h>
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#define MISC_MCELOG_MINOR 227
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#define NR_BANKS 6
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atomic_t mce_entry;
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static int mce_dont_init;
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/* 0: always panic, 1: panic if deadlock possible, 2: try to avoid panic,
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3: never panic or exit (for testing only) */
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static int tolerant = 1;
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static int banks;
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static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL };
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static unsigned long console_logged;
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static int notify_user;
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static int rip_msr;
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static int mce_bootlog = 1;
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static atomic_t mce_events;
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static char trigger[128];
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static char *trigger_argv[2] = { trigger, NULL };
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/*
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* Lockless MCE logging infrastructure.
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* This avoids deadlocks on printk locks without having to break locks. Also
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* separate MCEs from kernel messages to avoid bogus bug reports.
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*/
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struct mce_log mcelog = {
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MCE_LOG_SIGNATURE,
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MCE_LOG_LEN,
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};
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void mce_log(struct mce *mce)
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{
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unsigned next, entry;
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atomic_inc(&mce_events);
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mce->finished = 0;
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wmb();
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for (;;) {
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entry = rcu_dereference(mcelog.next);
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/* The rmb forces the compiler to reload next in each
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iteration */
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rmb();
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for (;;) {
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/* When the buffer fills up discard new entries. Assume
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that the earlier errors are the more interesting. */
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if (entry >= MCE_LOG_LEN) {
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set_bit(MCE_OVERFLOW, &mcelog.flags);
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return;
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}
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/* Old left over entry. Skip. */
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if (mcelog.entry[entry].finished) {
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entry++;
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continue;
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}
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break;
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}
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smp_rmb();
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next = entry + 1;
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if (cmpxchg(&mcelog.next, entry, next) == entry)
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break;
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}
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memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
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wmb();
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mcelog.entry[entry].finished = 1;
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wmb();
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if (!test_and_set_bit(0, &console_logged))
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notify_user = 1;
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}
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static void print_mce(struct mce *m)
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{
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printk(KERN_EMERG "\n"
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KERN_EMERG "HARDWARE ERROR\n"
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KERN_EMERG
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"CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
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m->cpu, m->mcgstatus, m->bank, m->status);
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if (m->rip) {
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printk(KERN_EMERG
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"RIP%s %02x:<%016Lx> ",
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!(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
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m->cs, m->rip);
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if (m->cs == __KERNEL_CS)
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print_symbol("{%s}", m->rip);
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printk("\n");
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}
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printk(KERN_EMERG "TSC %Lx ", m->tsc);
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if (m->addr)
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printk("ADDR %Lx ", m->addr);
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if (m->misc)
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printk("MISC %Lx ", m->misc);
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printk("\n");
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printk(KERN_EMERG "This is not a software problem!\n");
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printk(KERN_EMERG
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"Run through mcelog --ascii to decode and contact your hardware vendor\n");
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}
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static void mce_panic(char *msg, struct mce *backup, unsigned long start)
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{
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int i;
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oops_begin();
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for (i = 0; i < MCE_LOG_LEN; i++) {
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unsigned long tsc = mcelog.entry[i].tsc;
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if (time_before(tsc, start))
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continue;
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print_mce(&mcelog.entry[i]);
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if (backup && mcelog.entry[i].tsc == backup->tsc)
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backup = NULL;
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}
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if (backup)
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print_mce(backup);
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if (tolerant >= 3)
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printk("Fake panic: %s\n", msg);
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else
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panic(msg);
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}
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static int mce_available(struct cpuinfo_x86 *c)
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{
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return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
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}
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static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
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{
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if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
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m->rip = regs->rip;
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m->cs = regs->cs;
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} else {
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m->rip = 0;
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m->cs = 0;
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}
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if (rip_msr) {
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/* Assume the RIP in the MSR is exact. Is this true? */
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m->mcgstatus |= MCG_STATUS_EIPV;
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rdmsrl(rip_msr, m->rip);
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m->cs = 0;
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}
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}
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static void do_mce_trigger(void)
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{
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static atomic_t mce_logged;
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int events = atomic_read(&mce_events);
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if (events != atomic_read(&mce_logged) && trigger[0]) {
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/* Small race window, but should be harmless. */
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atomic_set(&mce_logged, events);
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call_usermodehelper(trigger, trigger_argv, NULL, -1);
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}
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}
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/*
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* The actual machine check handler
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*/
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void do_machine_check(struct pt_regs * regs, long error_code)
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{
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struct mce m, panicm;
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int nowayout = (tolerant < 1);
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int kill_it = 0;
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u64 mcestart = 0;
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int i;
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int panicm_found = 0;
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atomic_inc(&mce_entry);
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if (regs)
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notify_die(DIE_NMI, "machine check", regs, error_code, 18, SIGKILL);
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if (!banks)
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goto out2;
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memset(&m, 0, sizeof(struct mce));
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m.cpu = smp_processor_id();
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rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
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if (!(m.mcgstatus & MCG_STATUS_RIPV))
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kill_it = 1;
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rdtscll(mcestart);
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barrier();
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for (i = 0; i < banks; i++) {
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if (!bank[i])
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continue;
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m.misc = 0;
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m.addr = 0;
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m.bank = i;
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m.tsc = 0;
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rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
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if ((m.status & MCI_STATUS_VAL) == 0)
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continue;
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if (m.status & MCI_STATUS_EN) {
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/* In theory _OVER could be a nowayout too, but
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assume any overflowed errors were no fatal. */
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nowayout |= !!(m.status & MCI_STATUS_PCC);
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kill_it |= !!(m.status & MCI_STATUS_UC);
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}
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if (m.status & MCI_STATUS_MISCV)
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rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
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if (m.status & MCI_STATUS_ADDRV)
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rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
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mce_get_rip(&m, regs);
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if (error_code >= 0)
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rdtscll(m.tsc);
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wrmsrl(MSR_IA32_MC0_STATUS + i*4, 0);
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if (error_code != -2)
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mce_log(&m);
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/* Did this bank cause the exception? */
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/* Assume that the bank with uncorrectable errors did it,
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and that there is only a single one. */
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if ((m.status & MCI_STATUS_UC) && (m.status & MCI_STATUS_EN)) {
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panicm = m;
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panicm_found = 1;
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}
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* Never do anything final in the polling timer */
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if (!regs) {
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/* Normal interrupt context here. Call trigger for any new
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events. */
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do_mce_trigger();
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goto out;
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}
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/* If we didn't find an uncorrectable error, pick
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the last one (shouldn't happen, just being safe). */
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if (!panicm_found)
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panicm = m;
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if (nowayout)
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mce_panic("Machine check", &panicm, mcestart);
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if (kill_it) {
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int user_space = 0;
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if (m.mcgstatus & MCG_STATUS_RIPV)
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user_space = panicm.rip && (panicm.cs & 3);
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/* When the machine was in user space and the CPU didn't get
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confused it's normally not necessary to panic, unless you
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are paranoid (tolerant == 0)
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RED-PEN could be more tolerant for MCEs in idle,
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but most likely they occur at boot anyways, where
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it is best to just halt the machine. */
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if ((!user_space && (panic_on_oops || tolerant < 2)) ||
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(unsigned)current->pid <= 1)
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mce_panic("Uncorrected machine check", &panicm, mcestart);
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/* do_exit takes an awful lot of locks and has as
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slight risk of deadlocking. If you don't want that
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don't set tolerant >= 2 */
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if (tolerant < 3)
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do_exit(SIGBUS);
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}
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out:
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/* Last thing done in the machine check exception to clear state. */
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wrmsrl(MSR_IA32_MCG_STATUS, 0);
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out2:
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atomic_dec(&mce_entry);
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}
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#ifdef CONFIG_X86_MCE_INTEL
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/***
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* mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
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* @cpu: The CPU on which the event occured.
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* @status: Event status information
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*
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* This function should be called by the thermal interrupt after the
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* event has been processed and the decision was made to log the event
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* further.
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*
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* The status parameter will be saved to the 'status' field of 'struct mce'
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* and historically has been the register value of the
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* MSR_IA32_THERMAL_STATUS (Intel) msr.
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*/
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void mce_log_therm_throt_event(unsigned int cpu, __u64 status)
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{
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struct mce m;
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memset(&m, 0, sizeof(m));
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m.cpu = cpu;
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m.bank = MCE_THERMAL_BANK;
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m.status = status;
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rdtscll(m.tsc);
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mce_log(&m);
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}
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#endif /* CONFIG_X86_MCE_INTEL */
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/*
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* Periodic polling timer for "silent" machine check errors. If the
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* poller finds an MCE, poll 2x faster. When the poller finds no more
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* errors, poll 2x slower (up to check_interval seconds).
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*/
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static int check_interval = 5 * 60; /* 5 minutes */
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static int next_interval; /* in jiffies */
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static void mcheck_timer(struct work_struct *work);
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static DECLARE_DELAYED_WORK(mcheck_work, mcheck_timer);
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static void mcheck_check_cpu(void *info)
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{
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if (mce_available(¤t_cpu_data))
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do_machine_check(NULL, 0);
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}
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static void mcheck_timer(struct work_struct *work)
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{
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on_each_cpu(mcheck_check_cpu, NULL, 1, 1);
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/*
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* It's ok to read stale data here for notify_user and
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* console_logged as we'll simply get the updated versions
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* on the next mcheck_timer execution and atomic operations
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* on console_logged act as synchronization for notify_user
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* writes.
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*/
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if (notify_user && console_logged) {
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static unsigned long last_print;
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unsigned long now = jiffies;
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/* if we logged an MCE, reduce the polling interval */
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next_interval = max(next_interval/2, HZ/100);
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notify_user = 0;
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clear_bit(0, &console_logged);
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if (time_after_eq(now, last_print + (check_interval*HZ))) {
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last_print = now;
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printk(KERN_INFO "Machine check events logged\n");
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}
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} else {
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next_interval = min(next_interval*2, check_interval*HZ);
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}
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schedule_delayed_work(&mcheck_work, next_interval);
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}
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static __init int periodic_mcheck_init(void)
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{
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next_interval = check_interval * HZ;
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if (next_interval)
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schedule_delayed_work(&mcheck_work, next_interval);
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return 0;
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}
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__initcall(periodic_mcheck_init);
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/*
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* Initialize Machine Checks for a CPU.
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*/
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static void mce_init(void *dummy)
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{
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u64 cap;
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int i;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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banks = cap & 0xff;
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if (banks > NR_BANKS) {
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printk(KERN_INFO "MCE: warning: using only %d banks\n", banks);
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banks = NR_BANKS;
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}
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/* Use accurate RIP reporting if available. */
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if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9)
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rip_msr = MSR_IA32_MCG_EIP;
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/* Log the machine checks left over from the previous reset.
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This also clears all registers */
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do_machine_check(NULL, mce_bootlog ? -1 : -2);
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set_in_cr4(X86_CR4_MCE);
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if (cap & MCG_CTL_P)
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wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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for (i = 0; i < banks; i++) {
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wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
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wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
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}
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}
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/* Add per CPU specific workarounds here */
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static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
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{
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/* This should be disabled by the BIOS, but isn't always */
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if (c->x86_vendor == X86_VENDOR_AMD && c->x86 == 15) {
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/* disable GART TBL walk error reporting, which trips off
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incorrectly with the IOMMU & 3ware & Cerberus. */
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clear_bit(10, &bank[4]);
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/* Lots of broken BIOS around that don't clear them
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by default and leave crap in there. Don't log. */
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mce_bootlog = 0;
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}
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}
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static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c)
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{
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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mce_intel_feature_init(c);
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break;
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case X86_VENDOR_AMD:
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mce_amd_feature_init(c);
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break;
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default:
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break;
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}
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}
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/*
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* Called for each booted CPU to set up machine checks.
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* Must be called with preempt off.
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*/
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void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
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{
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static cpumask_t mce_cpus = CPU_MASK_NONE;
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mce_cpu_quirks(c);
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if (mce_dont_init ||
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cpu_test_and_set(smp_processor_id(), mce_cpus) ||
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!mce_available(c))
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return;
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mce_init(NULL);
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mce_cpu_features(c);
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}
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/*
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* Character device to read and clear the MCE log.
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*/
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static void collect_tscs(void *data)
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{
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unsigned long *cpu_tsc = (unsigned long *)data;
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rdtscll(cpu_tsc[smp_processor_id()]);
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}
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static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, loff_t *off)
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{
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unsigned long *cpu_tsc;
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static DECLARE_MUTEX(mce_read_sem);
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unsigned next;
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char __user *buf = ubuf;
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int i, err;
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cpu_tsc = kmalloc(NR_CPUS * sizeof(long), GFP_KERNEL);
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if (!cpu_tsc)
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return -ENOMEM;
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down(&mce_read_sem);
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next = rcu_dereference(mcelog.next);
|
|
|
|
/* Only supports full reads right now */
|
|
if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
|
|
up(&mce_read_sem);
|
|
kfree(cpu_tsc);
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = 0;
|
|
for (i = 0; i < next; i++) {
|
|
unsigned long start = jiffies;
|
|
while (!mcelog.entry[i].finished) {
|
|
if (time_after_eq(jiffies, start + 2)) {
|
|
memset(mcelog.entry + i,0, sizeof(struct mce));
|
|
goto timeout;
|
|
}
|
|
cpu_relax();
|
|
}
|
|
smp_rmb();
|
|
err |= copy_to_user(buf, mcelog.entry + i, sizeof(struct mce));
|
|
buf += sizeof(struct mce);
|
|
timeout:
|
|
;
|
|
}
|
|
|
|
memset(mcelog.entry, 0, next * sizeof(struct mce));
|
|
mcelog.next = 0;
|
|
|
|
synchronize_sched();
|
|
|
|
/* Collect entries that were still getting written before the synchronize. */
|
|
|
|
on_each_cpu(collect_tscs, cpu_tsc, 1, 1);
|
|
for (i = next; i < MCE_LOG_LEN; i++) {
|
|
if (mcelog.entry[i].finished &&
|
|
mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
|
|
err |= copy_to_user(buf, mcelog.entry+i, sizeof(struct mce));
|
|
smp_rmb();
|
|
buf += sizeof(struct mce);
|
|
memset(&mcelog.entry[i], 0, sizeof(struct mce));
|
|
}
|
|
}
|
|
up(&mce_read_sem);
|
|
kfree(cpu_tsc);
|
|
return err ? -EFAULT : buf - ubuf;
|
|
}
|
|
|
|
static int mce_ioctl(struct inode *i, struct file *f,unsigned int cmd, unsigned long arg)
|
|
{
|
|
int __user *p = (int __user *)arg;
|
|
if (!capable(CAP_SYS_ADMIN))
|
|
return -EPERM;
|
|
switch (cmd) {
|
|
case MCE_GET_RECORD_LEN:
|
|
return put_user(sizeof(struct mce), p);
|
|
case MCE_GET_LOG_LEN:
|
|
return put_user(MCE_LOG_LEN, p);
|
|
case MCE_GETCLEAR_FLAGS: {
|
|
unsigned flags;
|
|
do {
|
|
flags = mcelog.flags;
|
|
} while (cmpxchg(&mcelog.flags, flags, 0) != flags);
|
|
return put_user(flags, p);
|
|
}
|
|
default:
|
|
return -ENOTTY;
|
|
}
|
|
}
|
|
|
|
static const struct file_operations mce_chrdev_ops = {
|
|
.read = mce_read,
|
|
.ioctl = mce_ioctl,
|
|
};
|
|
|
|
static struct miscdevice mce_log_device = {
|
|
MISC_MCELOG_MINOR,
|
|
"mcelog",
|
|
&mce_chrdev_ops,
|
|
};
|
|
|
|
/*
|
|
* Old style boot options parsing. Only for compatibility.
|
|
*/
|
|
|
|
static int __init mcheck_disable(char *str)
|
|
{
|
|
mce_dont_init = 1;
|
|
return 1;
|
|
}
|
|
|
|
/* mce=off disables machine check. Note you can reenable it later
|
|
using sysfs.
|
|
mce=TOLERANCELEVEL (number, see above)
|
|
mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
|
|
mce=nobootlog Don't log MCEs from before booting. */
|
|
static int __init mcheck_enable(char *str)
|
|
{
|
|
if (*str == '=')
|
|
str++;
|
|
if (!strcmp(str, "off"))
|
|
mce_dont_init = 1;
|
|
else if (!strcmp(str, "bootlog") || !strcmp(str,"nobootlog"))
|
|
mce_bootlog = str[0] == 'b';
|
|
else if (isdigit(str[0]))
|
|
get_option(&str, &tolerant);
|
|
else
|
|
printk("mce= argument %s ignored. Please use /sys", str);
|
|
return 1;
|
|
}
|
|
|
|
__setup("nomce", mcheck_disable);
|
|
__setup("mce", mcheck_enable);
|
|
|
|
/*
|
|
* Sysfs support
|
|
*/
|
|
|
|
/* On resume clear all MCE state. Don't want to see leftovers from the BIOS.
|
|
Only one CPU is active at this time, the others get readded later using
|
|
CPU hotplug. */
|
|
static int mce_resume(struct sys_device *dev)
|
|
{
|
|
mce_init(NULL);
|
|
return 0;
|
|
}
|
|
|
|
/* Reinit MCEs after user configuration changes */
|
|
static void mce_restart(void)
|
|
{
|
|
if (next_interval)
|
|
cancel_delayed_work(&mcheck_work);
|
|
/* Timer race is harmless here */
|
|
on_each_cpu(mce_init, NULL, 1, 1);
|
|
next_interval = check_interval * HZ;
|
|
if (next_interval)
|
|
schedule_delayed_work(&mcheck_work, next_interval);
|
|
}
|
|
|
|
static struct sysdev_class mce_sysclass = {
|
|
.resume = mce_resume,
|
|
set_kset_name("machinecheck"),
|
|
};
|
|
|
|
DEFINE_PER_CPU(struct sys_device, device_mce);
|
|
|
|
/* Why are there no generic functions for this? */
|
|
#define ACCESSOR(name, var, start) \
|
|
static ssize_t show_ ## name(struct sys_device *s, char *buf) { \
|
|
return sprintf(buf, "%lx\n", (unsigned long)var); \
|
|
} \
|
|
static ssize_t set_ ## name(struct sys_device *s,const char *buf,size_t siz) { \
|
|
char *end; \
|
|
unsigned long new = simple_strtoul(buf, &end, 0); \
|
|
if (end == buf) return -EINVAL; \
|
|
var = new; \
|
|
start; \
|
|
return end-buf; \
|
|
} \
|
|
static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
|
|
|
|
/* TBD should generate these dynamically based on number of available banks */
|
|
ACCESSOR(bank0ctl,bank[0],mce_restart())
|
|
ACCESSOR(bank1ctl,bank[1],mce_restart())
|
|
ACCESSOR(bank2ctl,bank[2],mce_restart())
|
|
ACCESSOR(bank3ctl,bank[3],mce_restart())
|
|
ACCESSOR(bank4ctl,bank[4],mce_restart())
|
|
ACCESSOR(bank5ctl,bank[5],mce_restart())
|
|
|
|
static ssize_t show_trigger(struct sys_device *s, char *buf)
|
|
{
|
|
strcpy(buf, trigger);
|
|
strcat(buf, "\n");
|
|
return strlen(trigger) + 1;
|
|
}
|
|
|
|
static ssize_t set_trigger(struct sys_device *s,const char *buf,size_t siz)
|
|
{
|
|
char *p;
|
|
int len;
|
|
strncpy(trigger, buf, sizeof(trigger));
|
|
trigger[sizeof(trigger)-1] = 0;
|
|
len = strlen(trigger);
|
|
p = strchr(trigger, '\n');
|
|
if (*p) *p = 0;
|
|
return len;
|
|
}
|
|
|
|
static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
|
|
ACCESSOR(tolerant,tolerant,)
|
|
ACCESSOR(check_interval,check_interval,mce_restart())
|
|
static struct sysdev_attribute *mce_attributes[] = {
|
|
&attr_bank0ctl, &attr_bank1ctl, &attr_bank2ctl,
|
|
&attr_bank3ctl, &attr_bank4ctl, &attr_bank5ctl,
|
|
&attr_tolerant, &attr_check_interval, &attr_trigger,
|
|
NULL
|
|
};
|
|
|
|
/* Per cpu sysdev init. All of the cpus still share the same ctl bank */
|
|
static __cpuinit int mce_create_device(unsigned int cpu)
|
|
{
|
|
int err;
|
|
int i;
|
|
if (!mce_available(&cpu_data[cpu]))
|
|
return -EIO;
|
|
|
|
per_cpu(device_mce,cpu).id = cpu;
|
|
per_cpu(device_mce,cpu).cls = &mce_sysclass;
|
|
|
|
err = sysdev_register(&per_cpu(device_mce,cpu));
|
|
|
|
if (!err) {
|
|
for (i = 0; mce_attributes[i]; i++)
|
|
sysdev_create_file(&per_cpu(device_mce,cpu),
|
|
mce_attributes[i]);
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static void mce_remove_device(unsigned int cpu)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; mce_attributes[i]; i++)
|
|
sysdev_remove_file(&per_cpu(device_mce,cpu),
|
|
mce_attributes[i]);
|
|
sysdev_unregister(&per_cpu(device_mce,cpu));
|
|
memset(&per_cpu(device_mce, cpu).kobj, 0, sizeof(struct kobject));
|
|
}
|
|
|
|
/* Get notified when a cpu comes on/off. Be hotplug friendly. */
|
|
static int
|
|
mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
|
|
{
|
|
unsigned int cpu = (unsigned long)hcpu;
|
|
|
|
switch (action) {
|
|
case CPU_ONLINE:
|
|
case CPU_ONLINE_FROZEN:
|
|
mce_create_device(cpu);
|
|
break;
|
|
case CPU_DEAD:
|
|
case CPU_DEAD_FROZEN:
|
|
mce_remove_device(cpu);
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block mce_cpu_notifier = {
|
|
.notifier_call = mce_cpu_callback,
|
|
};
|
|
|
|
static __init int mce_init_device(void)
|
|
{
|
|
int err;
|
|
int i = 0;
|
|
|
|
if (!mce_available(&boot_cpu_data))
|
|
return -EIO;
|
|
err = sysdev_class_register(&mce_sysclass);
|
|
|
|
for_each_online_cpu(i) {
|
|
mce_create_device(i);
|
|
}
|
|
|
|
register_hotcpu_notifier(&mce_cpu_notifier);
|
|
misc_register(&mce_log_device);
|
|
return err;
|
|
}
|
|
|
|
device_initcall(mce_init_device);
|