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On ARC700 (and nSIM), user mode memory error triggers an L2 interrupt which is handled gracefully by kernel (or it tries to despite this being imprecise, and error could get charged to kernel itself). The offending task is killed and kernel moves on. NPS hardware however raises a Machine Check exception for same error which is NOT recoverable by kernel. This patch aligns kernel handling for nSIM case, to same as hardware by overriding the default user space bus error handler. Signed-off-by: Noam Camus <noamca@mellanox.com> Signed-off-by: Elad Kanfi <eladkan@mellanox.com> [vgupta: rewrote changelog] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
46 lines
1.4 KiB
Plaintext
46 lines
1.4 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.txt.
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#
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menuconfig ARC_PLAT_EZNPS
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bool "\"EZchip\" ARC dev platform"
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select CPU_BIG_ENDIAN
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select CLKSRC_NPS
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select EZNPS_GIC
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select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
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help
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Support for EZchip development platforms,
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based on ARC700 cores.
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We handle few flavors:
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- Hardware Emulator AKA HE which is FPGA based chassis
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- Simulator based on MetaWare nSIM
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- NPS400 chip based on ASIC
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config EZNPS_MTM_EXT
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bool "ARC-EZchip MTM Extensions"
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select CPUMASK_OFFSTACK
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depends on ARC_PLAT_EZNPS && SMP
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default y
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help
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Here we add new hierarchy for CPUs topology.
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We got:
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Core
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Thread
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At the new thread level each CPU represent one HW thread.
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At highest hierarchy each core contain 16 threads,
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any of them seem like CPU from Linux point of view.
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All threads within same core share the execution unit of the
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core and HW scheduler round robin between them.
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config EZNPS_MEM_ERROR_ALIGN
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bool "ARC-EZchip Memory error as an exception"
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depends on EZNPS_MTM_EXT
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default n
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help
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On the real chip of the NPS, user memory errors are handled
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as a machine check exception, which is fatal, whereas on
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simulator platform for NPS, is handled as a Level 2 interrupt
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(just a stock ARC700) which is recoverable. This option makes
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simulator behave like hardware.
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