Catalin Marinas
9a6655e49f
ARM: Improve the L2 cache performance when PL310 is used
...
With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop. This patch
conditionally defines the cache_wait() function.
Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when only CPU_V7 is defined.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2010-10-26 11:39:54 +05:30
..
2010-05-03 11:15:05 -07:00
2010-09-23 15:17:04 +01:00
2010-10-26 11:39:54 +05:30
2010-07-01 10:12:31 +01:00
2010-05-20 23:52:38 +01:00
2010-04-27 12:45:10 +02:00
2010-06-08 19:42:18 +01:00
2010-06-08 19:42:18 +01:00
2010-06-08 19:42:18 +01:00
2010-04-14 11:11:27 +01:00
2010-06-08 19:42:18 +01:00
2010-09-08 16:27:56 +01:00
2010-05-17 17:24:04 +01:00
2010-07-27 10:48:41 +01:00
2010-04-14 11:11:27 +01:00
2010-08-09 20:44:54 -07:00
2010-07-31 14:20:16 +01:00
2010-07-27 10:43:47 +01:00
2010-10-26 11:39:54 +05:30
2010-07-16 10:57:35 +01:00
2010-07-27 08:48:23 +01:00
2010-06-14 21:22:11 -04:00
2010-09-25 15:58:39 +01:00
2010-07-27 08:48:23 +01:00
2010-03-30 22:02:32 +09:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-09-17 16:44:24 +01:00
2010-07-27 10:48:42 +01:00
2010-07-27 10:48:42 +01:00
2010-05-08 10:44:30 +01:00
2010-07-27 10:43:48 +01:00
2010-07-27 10:43:48 +01:00