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99a5b2878b
Flushing caches sometimes requires anomaly workarounds which require supervisor-only insns. Normally we don't need to flush caches from userspace so this isn't a problem, but when gcc generates trampolines on the stack, we do. So add a new syscall for gcc to use modeled after the mips version. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
205 lines
4.3 KiB
C
205 lines
4.3 KiB
C
/*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BFIN_PTRACE_H
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#define _BFIN_PTRACE_H
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/*
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* GCC defines register number like this:
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* -----------------------------
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* 0 - 7 are data registers R0-R7
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* 8 - 15 are address registers P0-P7
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* 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
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* 32 - 33 A registers A0 & A1
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* 34 - status register
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* -----------------------------
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*
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* We follows above, except:
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* 32-33 --- Low 32-bit of A0&1
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* 34-35 --- High 8-bit of A0&1
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*/
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#ifndef __ASSEMBLY__
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struct task_struct;
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/* this struct defines the way the registers are stored on the
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stack during a system call. */
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struct pt_regs {
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long orig_pc;
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long ipend;
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long seqstat;
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long rete;
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long retn;
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long retx;
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long pc; /* PC == RETI */
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long rets;
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long reserved; /* Used as scratch during system calls */
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long astat;
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long lb1;
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long lb0;
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long lt1;
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long lt0;
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long lc1;
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long lc0;
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long a1w;
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long a1x;
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long a0w;
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long a0x;
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long b3;
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long b2;
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long b1;
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long b0;
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long l3;
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long l2;
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long l1;
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long l0;
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long m3;
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long m2;
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long m1;
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long m0;
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long i3;
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long i2;
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long i1;
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long i0;
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long usp;
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long fp;
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long p5;
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long p4;
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long p3;
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long p2;
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long p1;
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long p0;
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long r7;
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long r6;
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long r5;
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long r4;
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long r3;
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long r2;
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long r1;
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long r0;
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long orig_r0;
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long orig_p0;
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long syscfg;
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};
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/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13 /* ptrace signal */
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#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
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#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
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#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
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#define PS_S (0x0002)
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#ifdef __KERNEL__
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/* user_mode returns true if only one bit is set in IPEND, other than the
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master interrupt enable. */
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#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
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#define instruction_pointer(regs) ((regs)->pc)
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#define user_stack_pointer(regs) ((regs)->usp)
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#define profile_pc(regs) instruction_pointer(regs)
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extern void show_regs(struct pt_regs *);
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#define arch_has_single_step() (1)
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extern void user_enable_single_step(struct task_struct *child);
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extern void user_disable_single_step(struct task_struct *child);
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/* common code demands this function */
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#define ptrace_disable(child) user_disable_single_step(child)
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extern int is_user_addr_valid(struct task_struct *child,
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unsigned long start, unsigned long len);
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/*
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* Get the address of the live pt_regs for the specified task.
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* These are saved onto the top kernel stack when the process
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* is not running.
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*
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* Note: if a user thread is execve'd from kernel space, the
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* kernel stack will not be empty on entry to the kernel, so
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* ptracing these tasks will fail.
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*/
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#define task_pt_regs(task) \
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(struct pt_regs *) \
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((unsigned long)task_stack_page(task) + \
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(THREAD_SIZE - sizeof(struct pt_regs)))
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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/*
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* Offsets used by 'ptrace' system call interface.
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*/
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#define PT_R0 204
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#define PT_R1 200
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#define PT_R2 196
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#define PT_R3 192
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#define PT_R4 188
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#define PT_R5 184
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#define PT_R6 180
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#define PT_R7 176
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#define PT_P0 172
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#define PT_P1 168
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#define PT_P2 164
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#define PT_P3 160
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#define PT_P4 156
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#define PT_P5 152
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#define PT_FP 148
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#define PT_USP 144
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#define PT_I0 140
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#define PT_I1 136
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#define PT_I2 132
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#define PT_I3 128
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#define PT_M0 124
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#define PT_M1 120
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#define PT_M2 116
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#define PT_M3 112
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#define PT_L0 108
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#define PT_L1 104
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#define PT_L2 100
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#define PT_L3 96
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#define PT_B0 92
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#define PT_B1 88
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#define PT_B2 84
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#define PT_B3 80
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#define PT_A0X 76
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#define PT_A0W 72
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#define PT_A1X 68
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#define PT_A1W 64
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#define PT_LC0 60
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#define PT_LC1 56
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#define PT_LT0 52
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#define PT_LT1 48
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#define PT_LB0 44
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#define PT_LB1 40
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#define PT_ASTAT 36
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#define PT_RESERVED 32
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#define PT_RETS 28
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#define PT_PC 24
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#define PT_RETX 20
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#define PT_RETN 16
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#define PT_RETE 12
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#define PT_SEQSTAT 8
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#define PT_IPEND 4
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#define PT_ORIG_R0 208
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#define PT_ORIG_P0 212
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#define PT_SYSCFG 216
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#define PT_TEXT_ADDR 220
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#define PT_TEXT_END_ADDR 224
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#define PT_DATA_ADDR 228
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#define PT_FDPIC_EXEC 232
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#define PT_FDPIC_INTERP 236
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#define PT_LAST_PSEUDO PT_FDPIC_INTERP
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#endif /* _BFIN_PTRACE_H */
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