Andreas Herrmann a326e948c5 x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors
L3 cache size, associativity and shared_cpu information need to be
adapted to show information for an internal node instead of the
entire physical package.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-09-03 15:10:03 -07:00
..
2009-07-04 12:56:32 -07:00
2009-08-06 12:06:54 +03:00
2009-07-30 16:03:46 +09:30
2009-04-16 18:09:02 +02:00