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205 lines
6.0 KiB
C
205 lines
6.0 KiB
C
/*
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* arch/mips/vr41xx/nec-cmbvr4133/pci_fixup.c
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*
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* The NEC CMB-VR4133 Board specific PCI fixups.
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*
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* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
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* Alex Sapkov <asapkov@ru.mvista.com>
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*
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* 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Modified for support in 2.6
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* Author: Manish Lachwani (mlachwani@mvista.com)
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*
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/vr41xx/cmbvr4133.h>
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extern int vr4133_rockhopper;
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extern void ali_m1535plus_init(struct pci_dev *dev);
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extern void ali_m5229_init(struct pci_dev *dev);
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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/*
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* We have to reset AMD PCnet adapter on Rockhopper since
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* PMON leaves it enabled and generating interrupts. This leads
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* to a lock if some PCI device driver later enables the IRQ line
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* shared with PCnet and there is no AMD PCnet driver to catch its
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* interrupts.
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*/
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#ifdef CONFIG_ROCKHOPPER
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if (dev->vendor == PCI_VENDOR_ID_AMD &&
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dev->device == PCI_DEVICE_ID_AMD_LANCE) {
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inl(pci_resource_start(dev, 0) + 0x18);
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}
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#endif
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/*
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* we have to open the bridges' windows down to 0 because otherwise
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* we cannot access ISA south bridge I/O registers that get mapped from
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* 0. for example, 8259 PIC would be unaccessible without that
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*/
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if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) {
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pci_write_config_byte(dev, PCI_IO_BASE, 0);
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if(dev->bus->number == 0) {
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
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} else {
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1);
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}
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}
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return 0;
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}
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/*
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* M1535 IRQ mapping
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* Feel free to change this, although it shouldn't be needed
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*/
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#define M1535_IRQ_INTA 7
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#define M1535_IRQ_INTB 9
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#define M1535_IRQ_INTC 10
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#define M1535_IRQ_INTD 11
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#define M1535_IRQ_USB 9
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#define M1535_IRQ_IDE 14
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#define M1535_IRQ_IDE2 15
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#define M1535_IRQ_PS2 12
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#define M1535_IRQ_RTC 8
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#define M1535_IRQ_FDC 6
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#define M1535_IRQ_AUDIO 5
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#define M1535_IRQ_COM1 4
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#define M1535_IRQ_COM2 4
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#define M1535_IRQ_IRDA 3
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#define M1535_IRQ_KBD 1
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#define M1535_IRQ_TMR 0
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/* Rockhopper "slots" assignment; this is hard-coded ... */
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#define ROCKHOPPER_M5451_SLOT 1
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#define ROCKHOPPER_M1535_SLOT 2
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#define ROCKHOPPER_M5229_SLOT 11
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#define ROCKHOPPER_M5237_SLOT 15
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#define ROCKHOPPER_PMU_SLOT 12
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/* ... and hard-wired. */
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#define ROCKHOPPER_PCI1_SLOT 3
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#define ROCKHOPPER_PCI2_SLOT 4
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#define ROCKHOPPER_PCI3_SLOT 5
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#define ROCKHOPPER_PCI4_SLOT 6
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#define ROCKHOPPER_PCNET_SLOT 1
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#define M1535_IRQ_MASK(n) (1 << (n))
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#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \
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M1535_IRQ_MASK(M1535_IRQ_KBD) | \
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M1535_IRQ_MASK(M1535_IRQ_COM1) | \
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M1535_IRQ_MASK(M1535_IRQ_COM2) | \
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M1535_IRQ_MASK(M1535_IRQ_IRDA) | \
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M1535_IRQ_MASK(M1535_IRQ_RTC) | \
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M1535_IRQ_MASK(M1535_IRQ_FDC) | \
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M1535_IRQ_MASK(M1535_IRQ_PS2))
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#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \
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M1535_IRQ_MASK(M1535_IRQ_USB) | \
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M1535_IRQ_MASK(M1535_IRQ_INTA) | \
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M1535_IRQ_MASK(M1535_IRQ_INTB) | \
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M1535_IRQ_MASK(M1535_IRQ_INTC) | \
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M1535_IRQ_MASK(M1535_IRQ_INTD))
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struct irq_map_entry {
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u16 bus;
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u8 slot;
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u8 irq;
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};
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static struct irq_map_entry int_map[] = {
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{1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */
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{1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */
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{1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */
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{1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */
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{1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */
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{2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board
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ethernet */
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{2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */
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{2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */
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};
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static int pci_intlines[] =
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{ M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD };
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/* Determine the Rockhopper IRQ line number for the PCI device */
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int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot)
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{
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struct pci_bus *bus;
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int i;
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bus = dev->bus;
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if (bus == NULL)
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return -1;
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for (i = 0; i < sizeof (int_map) / sizeof (int_map[0]); i++) {
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if (int_map[i].bus == bus->number && int_map[i].slot == slot) {
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int line;
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for (line = 0; line < 4; line++)
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if (pci_intlines[line] == int_map[i].irq)
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break;
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if (line < 4)
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return pci_intlines[(line + (pin - 1)) % 4];
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else
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return int_map[i].irq;
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}
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}
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return -1;
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}
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#ifdef CONFIG_ROCKHOPPER
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void i8259_init(void)
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{
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outb(0x11, 0x20); /* Master ICW1 */
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outb(I8259_IRQ_BASE, 0x21); /* Master ICW2 */
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outb(0x04, 0x21); /* Master ICW3 */
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outb(0x01, 0x21); /* Master ICW4 */
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outb(0xff, 0x21); /* Master IMW */
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outb(0x11, 0xa0); /* Slave ICW1 */
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outb(I8259_IRQ_BASE + 8, 0xa1); /* Slave ICW2 */
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outb(0x02, 0xa1); /* Slave ICW3 */
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outb(0x01, 0xa1); /* Slave ICW4 */
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outb(0xff, 0xa1); /* Slave IMW */
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outb(0x00, 0x4d0);
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outb(0x02, 0x4d1); /* USB IRQ9 is level */
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}
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#endif
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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extern int pci_probe_only;
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pci_probe_only = 1;
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#ifdef CONFIG_ROCKHOPPER
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if( dev->bus->number == 1 && vr4133_rockhopper ) {
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if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT)
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dev->irq = CMBVR41XX_INTA_IRQ;
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else
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dev->irq = rockhopper_get_irq(dev, pin, slot);
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} else
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dev->irq = CMBVR41XX_INTA_IRQ;
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#else
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dev->irq = CMBVR41XX_INTA_IRQ;
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#endif
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return dev->irq;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, ali_m1535plus_init);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, ali_m5229_init);
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