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8aaf1dda42
These definitions use a ({}) construct to avoid some cases where
we were getting warnings about unused return values. We also
promote the definition to the common <asm/atomic.h>, since it applies
to both the 32- and 64-bit atomics.
In addition, define __HAVE_ARCH_CMPXCHG for TILE-Gx since it has
efficient direct atomic instructions.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
157 lines
4.4 KiB
C
157 lines
4.4 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* Do not include directly; use <asm/atomic.h>.
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*/
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#ifndef _ASM_TILE_ATOMIC_64_H
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#define _ASM_TILE_ATOMIC_64_H
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#ifndef __ASSEMBLY__
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#include <arch/spr_def.h>
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/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
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#define atomic_set(v, i) ((v)->counter = (i))
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/*
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* The smp_mb() operations throughout are to support the fact that
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* Linux requires memory barriers before and after the operation,
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* on any routine which updates memory and returns a value.
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*/
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static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
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{
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int val;
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__insn_mtspr(SPR_CMPEXCH_VALUE, o);
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smp_mb(); /* barrier for proper semantics */
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val = __insn_cmpexch4((void *)&v->counter, n);
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smp_mb(); /* barrier for proper semantics */
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return val;
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}
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static inline int atomic_xchg(atomic_t *v, int n)
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{
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int val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_exch4((void *)&v->counter, n);
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smp_mb(); /* barrier for proper semantics */
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return val;
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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__insn_fetchadd4((void *)&v->counter, i);
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_fetchadd4((void *)&v->counter, i) + i;
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barrier(); /* the "+ i" above will wait on memory */
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return val;
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}
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static inline int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int guess, oldval = v->counter;
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do {
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if (oldval == u)
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break;
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guess = oldval;
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oldval = atomic_cmpxchg(v, guess, guess + a);
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} while (guess != oldval);
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return oldval != u;
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}
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/* Now the true 64-bit operations. */
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic64_read(v) ((v)->counter)
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#define atomic64_set(v, i) ((v)->counter = (i))
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static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
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{
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long val;
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smp_mb(); /* barrier for proper semantics */
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__insn_mtspr(SPR_CMPEXCH_VALUE, o);
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val = __insn_cmpexch((void *)&v->counter, n);
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smp_mb(); /* barrier for proper semantics */
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return val;
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}
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static inline long atomic64_xchg(atomic64_t *v, long n)
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{
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long val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_exch((void *)&v->counter, n);
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smp_mb(); /* barrier for proper semantics */
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return val;
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}
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static inline void atomic64_add(long i, atomic64_t *v)
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{
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__insn_fetchadd((void *)&v->counter, i);
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}
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static inline long atomic64_add_return(long i, atomic64_t *v)
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{
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int val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_fetchadd((void *)&v->counter, i) + i;
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barrier(); /* the "+ i" above will wait on memory */
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return val;
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}
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static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long guess, oldval = v->counter;
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do {
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if (oldval == u)
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break;
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guess = oldval;
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oldval = atomic64_cmpxchg(v, guess, guess + a);
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} while (guess != oldval);
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return oldval != u;
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}
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#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
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#define atomic64_sub(i, v) atomic64_add(-(i), (v))
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#define atomic64_inc_return(v) atomic64_add_return(1, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
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#define atomic64_inc(v) atomic64_add(1, (v))
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#define atomic64_dec(v) atomic64_sub(1, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
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#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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/* Atomic dec and inc don't implement barrier, so provide them if needed. */
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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/* Define this to indicate that cmpxchg is an efficient operation. */
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#define __HAVE_ARCH_CMPXCHG
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_TILE_ATOMIC_64_H */
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