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c8df9a53e8
This fixes some two minor clk issues.
The first is a comparison where a byte will probably wrap around to 0 instead of being saturated to 255, shouldn't be triggered very often but need fixing.
The second is an attempt by the driver to adjust MCLK down to the maximum frequency according to the spec, so we don't accidentally overclock the PL18x block. None of the mach-{versatile|integrator|lh7a40x} that use it in-tree seem to have a problem with this (all are well below 100MHz, typically 33MHz), but some day there will be a problem.
This is not applied on top of the earlier mmci patch for race condition but rather a clean 2.6.25, but I guess it applies without major protests anyway.
Signed-off-by: Linus Walleij <triad@df.lth.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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