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https://github.com/FEX-Emu/linux.git
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5aa0769d08
This patch will only setup one clock, if free, and return this clock to the caller. The previous solution would setup both clocks with the same prescaler and divider and return PWM_CPR_CLKB, thus taking both clocks in the same call without the caller knowing. Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
410 lines
9.1 KiB
C
410 lines
9.1 KiB
C
#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/atmel_pwm.h>
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/*
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* This is a simple driver for the PWM controller found in various newer
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* Atmel SOCs, including the AVR32 series and the AT91sam9263.
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*
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* Chips with current Linux ports have only 4 PWM channels, out of max 32.
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* AT32UC3A and AT32UC3B chips have 7 channels (but currently no Linux).
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* Docs are inconsistent about the width of the channel counter registers;
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* it's at least 16 bits, but several places say 20 bits.
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*/
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#define PWM_NCHAN 4 /* max 32 */
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struct pwm {
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spinlock_t lock;
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struct platform_device *pdev;
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u32 mask;
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int irq;
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void __iomem *base;
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struct clk *clk;
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struct pwm_channel *channel[PWM_NCHAN];
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void (*handler[PWM_NCHAN])(struct pwm_channel *);
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};
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/* global PWM controller registers */
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#define PWM_MR 0x00
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#define PWM_ENA 0x04
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#define PWM_DIS 0x08
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#define PWM_SR 0x0c
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#define PWM_IER 0x10
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#define PWM_IDR 0x14
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#define PWM_IMR 0x18
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#define PWM_ISR 0x1c
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static inline void pwm_writel(const struct pwm *p, unsigned offset, u32 val)
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{
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__raw_writel(val, p->base + offset);
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}
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static inline u32 pwm_readl(const struct pwm *p, unsigned offset)
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{
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return __raw_readl(p->base + offset);
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}
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static inline void __iomem *pwmc_regs(const struct pwm *p, int index)
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{
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return p->base + 0x200 + index * 0x20;
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}
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static struct pwm *pwm;
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static void pwm_dumpregs(struct pwm_channel *ch, char *tag)
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{
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struct device *dev = &pwm->pdev->dev;
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dev_dbg(dev, "%s: mr %08x, sr %08x, imr %08x\n",
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tag,
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pwm_readl(pwm, PWM_MR),
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pwm_readl(pwm, PWM_SR),
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pwm_readl(pwm, PWM_IMR));
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dev_dbg(dev,
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"pwm ch%d - mr %08x, dty %u, prd %u, cnt %u\n",
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ch->index,
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pwm_channel_readl(ch, PWM_CMR),
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pwm_channel_readl(ch, PWM_CDTY),
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pwm_channel_readl(ch, PWM_CPRD),
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pwm_channel_readl(ch, PWM_CCNT));
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}
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/**
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* pwm_channel_alloc - allocate an unused PWM channel
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* @index: identifies the channel
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* @ch: structure to be initialized
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*
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* Drivers allocate PWM channels according to the board's wiring, and
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* matching board-specific setup code. Returns zero or negative errno.
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*/
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int pwm_channel_alloc(int index, struct pwm_channel *ch)
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{
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unsigned long flags;
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int status = 0;
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/* insist on PWM init, with this signal pinned out */
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if (!pwm || !(pwm->mask & 1 << index))
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return -ENODEV;
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if (index < 0 || index >= PWM_NCHAN || !ch)
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return -EINVAL;
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memset(ch, 0, sizeof *ch);
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spin_lock_irqsave(&pwm->lock, flags);
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if (pwm->channel[index])
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status = -EBUSY;
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else {
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clk_enable(pwm->clk);
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ch->regs = pwmc_regs(pwm, index);
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ch->index = index;
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/* REVISIT: ap7000 seems to go 2x as fast as we expect!! */
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ch->mck = clk_get_rate(pwm->clk);
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pwm->channel[index] = ch;
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pwm->handler[index] = NULL;
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/* channel and irq are always disabled when we return */
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pwm_writel(pwm, PWM_DIS, 1 << index);
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pwm_writel(pwm, PWM_IDR, 1 << index);
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return status;
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}
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EXPORT_SYMBOL(pwm_channel_alloc);
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static int pwmcheck(struct pwm_channel *ch)
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{
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int index;
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if (!pwm)
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return -ENODEV;
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if (!ch)
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return -EINVAL;
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index = ch->index;
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if (index < 0 || index >= PWM_NCHAN || pwm->channel[index] != ch)
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return -EINVAL;
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return index;
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}
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/**
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* pwm_channel_free - release a previously allocated channel
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* @ch: the channel being released
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*
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* The channel is completely shut down (counter and IRQ disabled),
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* and made available for re-use. Returns zero, or negative errno.
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*/
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int pwm_channel_free(struct pwm_channel *ch)
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{
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unsigned long flags;
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int t;
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm->channel[t] = NULL;
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pwm->handler[t] = NULL;
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/* channel and irq are always disabled when we return */
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pwm_writel(pwm, PWM_DIS, 1 << t);
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pwm_writel(pwm, PWM_IDR, 1 << t);
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clk_disable(pwm->clk);
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t = 0;
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(pwm_channel_free);
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int __pwm_channel_onoff(struct pwm_channel *ch, int enabled)
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{
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unsigned long flags;
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int t;
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/* OMITTED FUNCTIONALITY: starting several channels in synch */
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm_writel(pwm, enabled ? PWM_ENA : PWM_DIS, 1 << t);
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t = 0;
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pwm_dumpregs(ch, enabled ? "enable" : "disable");
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(__pwm_channel_onoff);
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/**
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* pwm_clk_alloc - allocate and configure CLKA or CLKB
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* @prescale: from 0..10, the power of two used to divide MCK
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* @div: from 1..255, the linear divisor to use
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*
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* Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated
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* clock will run with a period of (2^prescale * div) / MCK, or twice as
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* long if center aligned PWM output is used. The clock must later be
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* deconfigured using pwm_clk_free().
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*/
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int pwm_clk_alloc(unsigned prescale, unsigned div)
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{
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unsigned long flags;
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u32 mr;
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u32 val = (prescale << 8) | div;
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int ret = -EBUSY;
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if (prescale >= 10 || div == 0 || div > 255)
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return -EINVAL;
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spin_lock_irqsave(&pwm->lock, flags);
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mr = pwm_readl(pwm, PWM_MR);
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if ((mr & 0xffff) == 0) {
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mr |= val;
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ret = PWM_CPR_CLKA;
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} else if ((mr & (0xffff << 16)) == 0) {
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mr |= val << 16;
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ret = PWM_CPR_CLKB;
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}
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if (ret > 0)
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pwm_writel(pwm, PWM_MR, mr);
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spin_unlock_irqrestore(&pwm->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(pwm_clk_alloc);
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/**
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* pwm_clk_free - deconfigure and release CLKA or CLKB
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*
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* Reverses the effect of pwm_clk_alloc().
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*/
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void pwm_clk_free(unsigned clk)
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{
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unsigned long flags;
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u32 mr;
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spin_lock_irqsave(&pwm->lock, flags);
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mr = pwm_readl(pwm, PWM_MR);
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if (clk == PWM_CPR_CLKA)
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pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 0));
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if (clk == PWM_CPR_CLKB)
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pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 16));
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spin_unlock_irqrestore(&pwm->lock, flags);
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}
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EXPORT_SYMBOL(pwm_clk_free);
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/**
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* pwm_channel_handler - manage channel's IRQ handler
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* @ch: the channel
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* @handler: the handler to use, possibly NULL
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*
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* If the handler is non-null, the handler will be called after every
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* period of this PWM channel. If the handler is null, this channel
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* won't generate an IRQ.
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*/
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int pwm_channel_handler(struct pwm_channel *ch,
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void (*handler)(struct pwm_channel *ch))
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{
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unsigned long flags;
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int t;
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm->handler[t] = handler;
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pwm_writel(pwm, handler ? PWM_IER : PWM_IDR, 1 << t);
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t = 0;
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(pwm_channel_handler);
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static irqreturn_t pwm_irq(int id, void *_pwm)
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{
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struct pwm *p = _pwm;
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irqreturn_t handled = IRQ_NONE;
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u32 irqstat;
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int index;
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spin_lock(&p->lock);
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/* ack irqs, then handle them */
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irqstat = pwm_readl(pwm, PWM_ISR);
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while (irqstat) {
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struct pwm_channel *ch;
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void (*handler)(struct pwm_channel *ch);
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index = ffs(irqstat) - 1;
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irqstat &= ~(1 << index);
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ch = pwm->channel[index];
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handler = pwm->handler[index];
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if (handler && ch) {
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spin_unlock(&p->lock);
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handler(ch);
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spin_lock(&p->lock);
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handled = IRQ_HANDLED;
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}
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}
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spin_unlock(&p->lock);
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return handled;
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}
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static int __init pwm_probe(struct platform_device *pdev)
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{
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struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int irq = platform_get_irq(pdev, 0);
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u32 *mp = pdev->dev.platform_data;
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struct pwm *p;
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int status = -EIO;
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if (pwm)
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return -EBUSY;
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if (!r || irq < 0 || !mp || !*mp)
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return -ENODEV;
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if (*mp & ~((1<<PWM_NCHAN)-1)) {
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dev_warn(&pdev->dev, "mask 0x%x ... more than %d channels\n",
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*mp, PWM_NCHAN);
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return -EINVAL;
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}
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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spin_lock_init(&p->lock);
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p->pdev = pdev;
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p->mask = *mp;
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p->irq = irq;
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p->base = ioremap(r->start, r->end - r->start + 1);
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if (!p->base)
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goto fail;
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p->clk = clk_get(&pdev->dev, "pwm_clk");
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if (IS_ERR(p->clk)) {
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status = PTR_ERR(p->clk);
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p->clk = NULL;
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goto fail;
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}
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status = request_irq(irq, pwm_irq, 0, pdev->name, p);
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if (status < 0)
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goto fail;
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pwm = p;
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platform_set_drvdata(pdev, p);
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return 0;
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fail:
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if (p->clk)
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clk_put(p->clk);
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if (p->base)
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iounmap(p->base);
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kfree(p);
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return status;
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}
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static int __exit pwm_remove(struct platform_device *pdev)
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{
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struct pwm *p = platform_get_drvdata(pdev);
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if (p != pwm)
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return -EINVAL;
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clk_enable(pwm->clk);
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pwm_writel(pwm, PWM_DIS, (1 << PWM_NCHAN) - 1);
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pwm_writel(pwm, PWM_IDR, (1 << PWM_NCHAN) - 1);
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clk_disable(pwm->clk);
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pwm = NULL;
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free_irq(p->irq, p);
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clk_put(p->clk);
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iounmap(p->base);
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kfree(p);
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return 0;
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}
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static struct platform_driver atmel_pwm_driver = {
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.driver = {
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.name = "atmel_pwm",
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.owner = THIS_MODULE,
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},
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.remove = __exit_p(pwm_remove),
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/* NOTE: PWM can keep running in AVR32 "idle" and "frozen" states;
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* and all AT91sam9263 states, albeit at reduced clock rate if
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* MCK becomes the slow clock (i.e. what Linux labels STR).
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*/
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};
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static int __init pwm_init(void)
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{
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return platform_driver_probe(&atmel_pwm_driver, pwm_probe);
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}
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module_init(pwm_init);
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static void __exit pwm_exit(void)
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{
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platform_driver_unregister(&atmel_pwm_driver);
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}
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module_exit(pwm_exit);
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MODULE_DESCRIPTION("Driver for AT32/AT91 PWM module");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:atmel_pwm");
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