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a95d67f87e
Here's the new ptrace BTS API that supports two different overflow handling mechanisms (wrap-around and buffer-full-signal) to support two different use cases (debugging and profiling). It further combines buffer allocation and configuration. Opens: - memory rlimit - overflow signal What would be the right signal to use? Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
466 lines
10 KiB
C
466 lines
10 KiB
C
/*
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* Debug Store support
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*
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* This provides a low-level interface to the hardware's Debug Store
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* feature that is used for last branch recording (LBR) and
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* precise-event based sampling (PEBS).
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*
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* Different architectures use a different DS layout/pointer size.
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* The below functions therefore work on a void*.
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*
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*
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* Since there is no user for PEBS, yet, only LBR (or branch
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* trace store, BTS) is supported.
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*
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*
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* Copyright (C) 2007 Intel Corporation.
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* Markus Metzger <markus.t.metzger@intel.com>, Dec 2007
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*/
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#include <asm/ds.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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/*
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* Debug Store (DS) save area configuration (see Intel64 and IA32
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* Architectures Software Developer's Manual, section 18.5)
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*
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* The DS configuration consists of the following fields; different
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* architetures vary in the size of those fields.
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* - double-word aligned base linear address of the BTS buffer
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* - write pointer into the BTS buffer
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* - end linear address of the BTS buffer (one byte beyond the end of
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* the buffer)
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* - interrupt pointer into BTS buffer
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* (interrupt occurs when write pointer passes interrupt pointer)
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* - double-word aligned base linear address of the PEBS buffer
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* - write pointer into the PEBS buffer
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* - end linear address of the PEBS buffer (one byte beyond the end of
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* the buffer)
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* - interrupt pointer into PEBS buffer
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* (interrupt occurs when write pointer passes interrupt pointer)
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* - value to which counter is reset following counter overflow
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*
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* On later architectures, the last branch recording hardware uses
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* 64bit pointers even in 32bit mode.
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*
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*
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* Branch Trace Store (BTS) records store information about control
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* flow changes. They at least provide the following information:
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* - source linear address
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* - destination linear address
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*
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* Netburst supported a predicated bit that had been dropped in later
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* architectures. We do not suppor it.
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*
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*
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* In order to abstract from the actual DS and BTS layout, we describe
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* the access to the relevant fields.
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* Thanks to Andi Kleen for proposing this design.
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*
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* The implementation, however, is not as general as it might seem. In
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* order to stay somewhat simple and efficient, we assume an
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* underlying unsigned type (mostly a pointer type) and we expect the
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* field to be at least as big as that type.
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*/
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/*
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* A special from_ip address to indicate that the BTS record is an
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* info record that needs to be interpreted or skipped.
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*/
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#define BTS_ESCAPE_ADDRESS (-1)
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/*
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* A field access descriptor
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*/
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struct access_desc {
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unsigned char offset;
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unsigned char size;
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};
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/*
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* The configuration for a particular DS/BTS hardware implementation.
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*/
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struct ds_configuration {
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/* the DS configuration */
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unsigned char sizeof_ds;
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struct access_desc bts_buffer_base;
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struct access_desc bts_index;
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struct access_desc bts_absolute_maximum;
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struct access_desc bts_interrupt_threshold;
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/* the BTS configuration */
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unsigned char sizeof_bts;
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struct access_desc from_ip;
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struct access_desc to_ip;
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/* BTS variants used to store additional information like
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timestamps */
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struct access_desc info_type;
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struct access_desc info_data;
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unsigned long debugctl_mask;
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};
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/*
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* The global configuration used by the below accessor functions
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*/
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static struct ds_configuration ds_cfg;
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/*
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* Accessor functions for some DS and BTS fields using the above
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* global ptrace_bts_cfg.
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*/
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static inline void *get_bts_buffer_base(char *base)
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{
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return *(void **)(base + ds_cfg.bts_buffer_base.offset);
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}
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static inline void set_bts_buffer_base(char *base, void *value)
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{
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(*(void **)(base + ds_cfg.bts_buffer_base.offset)) = value;
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}
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static inline void *get_bts_index(char *base)
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{
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return *(void **)(base + ds_cfg.bts_index.offset);
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}
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static inline void set_bts_index(char *base, void *value)
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{
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(*(void **)(base + ds_cfg.bts_index.offset)) = value;
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}
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static inline void *get_bts_absolute_maximum(char *base)
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{
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return *(void **)(base + ds_cfg.bts_absolute_maximum.offset);
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}
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static inline void set_bts_absolute_maximum(char *base, void *value)
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{
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(*(void **)(base + ds_cfg.bts_absolute_maximum.offset)) = value;
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}
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static inline void *get_bts_interrupt_threshold(char *base)
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{
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return *(void **)(base + ds_cfg.bts_interrupt_threshold.offset);
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}
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static inline void set_bts_interrupt_threshold(char *base, void *value)
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{
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(*(void **)(base + ds_cfg.bts_interrupt_threshold.offset)) = value;
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}
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static inline long get_from_ip(char *base)
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{
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return *(long *)(base + ds_cfg.from_ip.offset);
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}
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static inline void set_from_ip(char *base, long value)
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{
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(*(long *)(base + ds_cfg.from_ip.offset)) = value;
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}
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static inline long get_to_ip(char *base)
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{
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return *(long *)(base + ds_cfg.to_ip.offset);
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}
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static inline void set_to_ip(char *base, long value)
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{
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(*(long *)(base + ds_cfg.to_ip.offset)) = value;
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}
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static inline unsigned char get_info_type(char *base)
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{
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return *(unsigned char *)(base + ds_cfg.info_type.offset);
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}
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static inline void set_info_type(char *base, unsigned char value)
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{
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(*(unsigned char *)(base + ds_cfg.info_type.offset)) = value;
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}
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static inline unsigned long get_info_data(char *base)
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{
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return *(unsigned long *)(base + ds_cfg.info_data.offset);
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}
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static inline void set_info_data(char *base, unsigned long value)
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{
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(*(unsigned long *)(base + ds_cfg.info_data.offset)) = value;
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}
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int ds_allocate(void **dsp, size_t bts_size_in_bytes)
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{
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size_t bts_size_in_records;
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void *bts;
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void *ds;
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if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
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return -EOPNOTSUPP;
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if (bts_size_in_bytes < 0)
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return -EINVAL;
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bts_size_in_records =
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bts_size_in_bytes / ds_cfg.sizeof_bts;
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bts_size_in_bytes =
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bts_size_in_records * ds_cfg.sizeof_bts;
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if (bts_size_in_bytes <= 0)
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return -EINVAL;
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bts = kzalloc(bts_size_in_bytes, GFP_KERNEL);
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if (!bts)
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return -ENOMEM;
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ds = kzalloc(ds_cfg.sizeof_ds, GFP_KERNEL);
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if (!ds) {
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kfree(bts);
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return -ENOMEM;
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}
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set_bts_buffer_base(ds, bts);
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set_bts_index(ds, bts);
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set_bts_absolute_maximum(ds, bts + bts_size_in_bytes);
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set_bts_interrupt_threshold(ds, bts + bts_size_in_bytes + 1);
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*dsp = ds;
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return 0;
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}
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int ds_free(void **dsp)
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{
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if (*dsp)
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kfree(get_bts_buffer_base(*dsp));
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kfree(*dsp);
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*dsp = 0;
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return 0;
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}
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int ds_get_bts_size(void *ds)
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{
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size_t size_in_bytes;
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if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
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return -EOPNOTSUPP;
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if (!ds)
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return 0;
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size_in_bytes =
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get_bts_absolute_maximum(ds) -
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get_bts_buffer_base(ds);
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return size_in_bytes;
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}
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int ds_get_bts_end(void *ds)
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{
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size_t size_in_bytes = ds_get_bts_size(ds);
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if (size_in_bytes <= 0)
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return size_in_bytes;
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return size_in_bytes / ds_cfg.sizeof_bts;
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}
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int ds_get_bts_index(void *ds)
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{
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size_t index_offset_in_bytes;
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if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
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return -EOPNOTSUPP;
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index_offset_in_bytes =
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get_bts_index(ds) -
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get_bts_buffer_base(ds);
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return index_offset_in_bytes / ds_cfg.sizeof_bts;
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}
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int ds_set_overflow(void *ds, int method)
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{
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switch (method) {
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case DS_O_SIGNAL:
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return -EOPNOTSUPP;
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case DS_O_WRAP:
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return 0;
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default:
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return -EINVAL;
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}
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}
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int ds_get_overflow(void *ds)
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{
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return DS_O_WRAP;
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}
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int ds_clear(void *ds)
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{
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int bts_size = ds_get_bts_size(ds);
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void *bts_base;
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if (bts_size <= 0)
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return bts_size;
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bts_base = get_bts_buffer_base(ds);
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memset(bts_base, 0, bts_size);
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set_bts_index(ds, bts_base);
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return 0;
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}
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int ds_read_bts(void *ds, size_t index, struct bts_struct *out)
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{
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void *bts;
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if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
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return -EOPNOTSUPP;
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if (index < 0)
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return -EINVAL;
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if (index >= ds_get_bts_size(ds))
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return -EINVAL;
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bts = get_bts_buffer_base(ds);
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bts = (char *)bts + (index * ds_cfg.sizeof_bts);
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memset(out, 0, sizeof(*out));
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if (get_from_ip(bts) == BTS_ESCAPE_ADDRESS) {
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out->qualifier = get_info_type(bts);
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out->variant.jiffies = get_info_data(bts);
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} else {
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out->qualifier = BTS_BRANCH;
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out->variant.lbr.from_ip = get_from_ip(bts);
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out->variant.lbr.to_ip = get_to_ip(bts);
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}
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return 0;
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}
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int ds_write_bts(void *ds, const struct bts_struct *in)
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{
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void *bts;
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if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
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return -EOPNOTSUPP;
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if (ds_get_bts_size(ds) <= 0)
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return -ENXIO;
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bts = get_bts_index(ds);
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memset(bts, 0, ds_cfg.sizeof_bts);
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switch (in->qualifier) {
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case BTS_INVALID:
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break;
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case BTS_BRANCH:
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set_from_ip(bts, in->variant.lbr.from_ip);
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set_to_ip(bts, in->variant.lbr.to_ip);
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break;
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case BTS_TASK_ARRIVES:
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case BTS_TASK_DEPARTS:
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set_from_ip(bts, BTS_ESCAPE_ADDRESS);
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set_info_type(bts, in->qualifier);
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set_info_data(bts, in->variant.jiffies);
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break;
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default:
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return -EINVAL;
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}
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bts = (char *)bts + ds_cfg.sizeof_bts;
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if (bts >= get_bts_absolute_maximum(ds))
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bts = get_bts_buffer_base(ds);
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set_bts_index(ds, bts);
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return 0;
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}
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unsigned long ds_debugctl_mask(void)
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{
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return ds_cfg.debugctl_mask;
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}
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#ifdef __i386__
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static const struct ds_configuration ds_cfg_netburst = {
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.sizeof_ds = 9 * 4,
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.bts_buffer_base = { 0, 4 },
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.bts_index = { 4, 4 },
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.bts_absolute_maximum = { 8, 4 },
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.bts_interrupt_threshold = { 12, 4 },
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.sizeof_bts = 3 * 4,
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.from_ip = { 0, 4 },
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.to_ip = { 4, 4 },
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.info_type = { 4, 1 },
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.info_data = { 8, 4 },
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.debugctl_mask = (1<<2)|(1<<3)
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};
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static const struct ds_configuration ds_cfg_pentium_m = {
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.sizeof_ds = 9 * 4,
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.bts_buffer_base = { 0, 4 },
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.bts_index = { 4, 4 },
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.bts_absolute_maximum = { 8, 4 },
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.bts_interrupt_threshold = { 12, 4 },
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.sizeof_bts = 3 * 4,
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.from_ip = { 0, 4 },
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.to_ip = { 4, 4 },
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.info_type = { 4, 1 },
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.info_data = { 8, 4 },
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.debugctl_mask = (1<<6)|(1<<7)
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};
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#endif /* _i386_ */
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static const struct ds_configuration ds_cfg_core2 = {
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.sizeof_ds = 9 * 8,
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.bts_buffer_base = { 0, 8 },
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.bts_index = { 8, 8 },
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.bts_absolute_maximum = { 16, 8 },
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.bts_interrupt_threshold = { 24, 8 },
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.sizeof_bts = 3 * 8,
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.from_ip = { 0, 8 },
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.to_ip = { 8, 8 },
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.info_type = { 8, 1 },
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.info_data = { 16, 8 },
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.debugctl_mask = (1<<6)|(1<<7)|(1<<9)
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};
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static inline void
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ds_configure(const struct ds_configuration *cfg)
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{
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ds_cfg = *cfg;
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}
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void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
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{
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switch (c->x86) {
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case 0x6:
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switch (c->x86_model) {
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#ifdef __i386__
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case 0xD:
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case 0xE: /* Pentium M */
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ds_configure(&ds_cfg_pentium_m);
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break;
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#endif /* _i386_ */
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case 0xF: /* Core2 */
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ds_configure(&ds_cfg_core2);
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break;
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default:
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/* sorry, don't know about them */
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break;
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}
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break;
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case 0xF:
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switch (c->x86_model) {
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#ifdef __i386__
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case 0x0:
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case 0x1:
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case 0x2: /* Netburst */
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ds_configure(&ds_cfg_netburst);
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break;
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#endif /* _i386_ */
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default:
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/* sorry, don't know about them */
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break;
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}
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break;
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default:
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/* sorry, don't know about them */
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break;
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}
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}
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