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ad4a38d218
Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if something went wrong instead of continuing in unknown condition. There is not much we can do if a PLL lock never ends, we are running in SRAM and we will not be able to connect back the sdram or ddram in order to be able to fire up a message or just panic. As a bonus, not decounting the timeout register in slow clock mode reduce cumulated suspend time and resume time from ~17ms to ~15ms. Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>