Russell King b059bdc393 ARM: entry: rejig register allocation in exception entry handlers
This allows us to avoid moving registers twice to work around the
clobbered registers when we add calls to trace_hardirqs_{on,off}.

Ensure that all SVC handlers return with SPSR in r5 for consistency.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-30 11:04:59 +01:00
..
2011-05-25 23:04:35 +08:00
2011-03-31 11:26:23 -03:00
2011-05-14 21:36:55 +01:00
2011-03-31 11:26:23 -03:00