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273 lines
6.9 KiB
C
273 lines
6.9 KiB
C
/*
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* Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Routines for generic manipulation of the interrupts found on the MIPS
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* Atlas board.
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*
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*/
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/kernel.h>
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#include <asm/gdb-stub.h>
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#include <asm/io.h>
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#include <asm/irq_cpu.h>
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#include <asm/msc01_ic.h>
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#include <asm/mips-boards/atlas.h>
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#include <asm/mips-boards/atlasint.h>
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#include <asm/mips-boards/generic.h>
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static struct atlas_ictrl_regs *atlas_hw0_icregs;
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#if 0
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#define DEBUG_INT(x...) printk(x)
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#else
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#define DEBUG_INT(x...)
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#endif
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void disable_atlas_irq(unsigned int irq_nr)
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{
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atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
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iob();
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}
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void enable_atlas_irq(unsigned int irq_nr)
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{
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atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
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iob();
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}
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static void end_atlas_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_atlas_irq(irq);
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}
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static struct irq_chip atlas_irq_type = {
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.name = "Atlas",
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.ack = disable_atlas_irq,
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.mask = disable_atlas_irq,
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.mask_ack = disable_atlas_irq,
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.unmask = enable_atlas_irq,
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.eoi = enable_atlas_irq,
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.end = end_atlas_irq,
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};
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static inline int ls1bit32(unsigned int x)
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{
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int b = 31, s;
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s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
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s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
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s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
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s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
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s = 1; if (x << 1 == 0) s = 0; b -= s;
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return b;
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}
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static inline void atlas_hw0_irqdispatch(void)
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{
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unsigned long int_status;
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int irq;
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int_status = atlas_hw0_icregs->intstatus;
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/* if int_status == 0, then the interrupt has already been cleared */
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if (unlikely(int_status == 0))
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return;
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irq = ATLAS_INT_BASE + ls1bit32(int_status);
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DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
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do_IRQ(irq);
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}
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static inline int clz(unsigned long x)
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{
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__asm__(
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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" .set pop \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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/*
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* Version of ffs that only looks at bits 12..15.
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*/
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static inline unsigned int irq_ffs(unsigned int pending)
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{
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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return -clz(pending) + 31 - CAUSEB_IP;
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#else
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unsigned int a0 = 7;
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unsigned int t0;
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t0 = s0 & 0xf000;
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t0 = t0 < 1;
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t0 = t0 << 2;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0xc000;
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t0 = t0 < 1;
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t0 = t0 << 1;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0x8000;
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t0 = t0 < 1;
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//t0 = t0 << 2;
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a0 = a0 - t0;
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//s0 = s0 << t0;
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return a0;
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#endif
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}
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/*
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* IRQs on the Atlas board look basically like (all external interrupt
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* sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software 0 (reschedule IPI on MT)
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* 1 Software 1 (remote call IPI on MT)
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* 2 Combined Atlas hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Software 0
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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irq = irq_ffs(pending);
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if (irq == MIPSCPU_INT_ATLAS)
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atlas_hw0_irqdispatch();
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else if (irq >= 0)
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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static inline void init_atlas_irqs(int base)
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{
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int i;
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atlas_hw0_icregs = (struct atlas_ictrl_regs *)
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ioremap(ATLAS_ICTRL_REGS_BASE,
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sizeof(struct atlas_ictrl_regs *));
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/*
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* Mask out all interrupt by writing "1" to all bit position in
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* the interrupt reset reg.
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*/
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atlas_hw0_icregs->intrsten = 0xffffffff;
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for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
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set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
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}
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static struct irqaction atlasirq = {
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.handler = no_action,
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.name = "Atlas cascade"
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};
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msc_irqmap_t __initdata msc_irqmap[] = {
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{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
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};
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int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
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msc_irqmap_t __initdata msc_eicirqmap[] = {
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{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
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};
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int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
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void __init arch_init_irq(void)
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{
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init_atlas_irqs(ATLAS_INT_BASE);
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_FPGA4:
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case MIPS_REVISION_CORID_CORE_24K:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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if (cpu_has_veic)
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init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
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msc_eicirqmap, msc_nr_eicirqs);
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else
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init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
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msc_irqmap, msc_nr_irqs);
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}
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
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setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
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} else if (cpu_has_vint) {
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set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
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&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
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#else /* Not SMTC */
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setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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} else
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setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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}
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