Original code was assuming that the CSPI1 pins on the
MX31PDK were the primary pin function, which is incorrect.
On MX31PDK board these are the pins that provide CSPI1 functionality:
DSR_DCE1 (ALT mode 1) --> CSPI1_CLK
RI_DCE1 (ALT mode 1) --> CSPI1_RDY
DTR_DTE1 -->CSI1_MOSI
DSR_DTE1 --> CSPI1_MISO
DTR_DCE2 ---> CSPI1_SS2
The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM.
This patch fixes the CSPI1 IOMUX and makes the LCD to be functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
b2a08e3e46