Catalin Marinas b3901d54dc arm64: Process management ... The patch adds support for thread creation and context switching. The context switching CPU specific code is introduced with the CPU support patch (part of the arch/arm64/mm/proc.S file). AArch64 supports ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable via the ID_AA64AFR0_EL1 register). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>		2012-09-17 13:41:58 +01:00
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context.c	arm64: Process management	2012-09-17 13:41:58 +01:00
copypage.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
extable.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
fault.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
init.c
mm.h	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
mmap.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
mmu.c
pgd.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
proc-macros.S