mirror of
https://github.com/FEX-Emu/linux.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
207 lines
5.0 KiB
C
207 lines
5.0 KiB
C
/*
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* arch/sh/mm/cache-sh7705.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2004 Alex Song
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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/* The 32KB cache on the SH7705 suffers from the same synonym problem
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* as SH4 CPUs */
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#define __pte_offset(address) \
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset(dir, address) ((pte_t *) pmd_page_kernel(*(dir)) + \
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__pte_offset(address))
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static inline void cache_wback_all(void)
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{
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unsigned long ways, waysize, addrstart;
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ways = cpu_data->dcache.ways;
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waysize = cpu_data->dcache.sets;
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waysize <<= cpu_data->dcache.entry_shift;
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long addr;
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for (addr = addrstart;
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addr < addrstart + waysize;
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addr += cpu_data->dcache.linesz) {
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unsigned long data;
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int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
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data = ctrl_inl(addr);
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if ((data & v) == v)
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ctrl_outl(data & ~v, addr);
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}
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addrstart += cpu_data->dcache.way_incr;
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} while (--ways);
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}
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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* Called from kernel/module.c:sys_init_module and routine for a.out format.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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__flush_wback_region((void *)start, end - start);
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}
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/*
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* Writeback&Invalidate the D-cache of the page
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*/
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static void __flush_dcache_page(unsigned long phys)
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{
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unsigned long ways, waysize, addrstart;
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unsigned long flags;
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phys |= SH_CACHE_VALID;
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/*
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* Here, phys is the physical address of the page. We check all the
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* tags in the cache for those with the same page number as this page
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* (by masking off the lowest 2 bits of the 19-bit tag; these bits are
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* derived from the offset within in the 4k page). Matching valid
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* entries are invalidated.
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*
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* Since 2 bits of the cache index are derived from the virtual page
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* number, knowing this would reduce the number of cache entries to be
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* searched by a factor of 4. However this function exists to deal with
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* potential cache aliasing, therefore the optimisation is probably not
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* possible.
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*/
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local_irq_save(flags);
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jump_to_P2();
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ways = cpu_data->dcache.ways;
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waysize = cpu_data->dcache.sets;
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waysize <<= cpu_data->dcache.entry_shift;
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long addr;
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for (addr = addrstart;
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addr < addrstart + waysize;
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addr += cpu_data->dcache.linesz) {
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unsigned long data;
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data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
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if (data == phys) {
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data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
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ctrl_outl(data, addr);
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}
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}
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addrstart += cpu_data->dcache.way_incr;
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} while (--ways);
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back_to_P1();
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local_irq_restore(flags);
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}
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*/
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void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_mapped, &page->flags))
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__flush_dcache_page(PHYSADDR(page_address(page)));
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}
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void flush_cache_all(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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jump_to_P2();
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cache_wback_all();
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back_to_P1();
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local_irq_restore(flags);
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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/* Is there any good way? */
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/* XXX: possibly call flush_cache_range for each vm area */
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flush_cache_all();
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}
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/*
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* Write back and invalidate D-caches.
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*
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* START, END: Virtual Address (U0 address)
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*
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* NOTE: We need to flush the _physical_ page entry.
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* Flushing the cache lines for U0 only isn't enough.
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* We need to flush for P1 too, which may contain aliases.
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*/
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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/*
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* We could call flush_cache_page for the pages of these range,
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* but it's not efficient (scan the caches all the time...).
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*
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* We can't use A-bit magic, as there's the case we don't have
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* valid entry on TLB.
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*/
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flush_cache_all();
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}
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/*
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* Write back and invalidate I/D-caches for the page.
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*
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* ADDRESS: Virtual Address (U0 address)
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*/
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void flush_cache_page(struct vm_area_struct *vma, unsigned long address, unsigned long pfn)
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{
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__flush_dcache_page(pfn << PAGE_SHIFT);
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}
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/*
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* This is called when a page-cache page is about to be mapped into a
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* user process' address space. It offers an opportunity for a
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* port to ensure d-cache/i-cache coherency if necessary.
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*
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* Not entirely sure why this is necessary on SH3 with 32K cache but
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* without it we get occasional "Memory fault" when loading a program.
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*/
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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__flush_purge_region(page_address(page), PAGE_SIZE);
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}
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