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b64f87c16f
The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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.. | ||
asm-offsets.c | ||
cpu_setup_power4.S | ||
entry.S | ||
head_4xx.S | ||
head_8xx.S | ||
head_44x.S | ||
head_booke.h | ||
head_fsl_booke.S | ||
head.S | ||
machine_kexec.c | ||
Makefile | ||
misc.S | ||
pci.c | ||
ppc_htab.c | ||
ppc_ksyms.c | ||
ppc-stub.c | ||
relocate_kernel.S | ||
rio.c | ||
semaphore.c | ||
setup.c | ||
smp-tbsync.c | ||
smp.c | ||
softemu8xx.c | ||
time.c | ||
traps.c | ||
vmlinux.lds.S |