Gregory CLEMENT b6dda00cdd ARM: mvebu: use the virtual CPU registers to access coherency registers ... The Armada XP provides a mechanism called "virtual CPU registers" or "per-CPU register banking", to access the per-CPU registers of the current CPU, without having to worry about finding on which CPU we're running. CPU0 has its registers at 0x21800, CPU1 at 0x21900, CPU2 at 0x21A00 and CPU3 at 0x21B00. The virtual registers accessing the current CPU registers are at 0x21000. However, in the Device Tree node that provides the register addresses for the coherency unit (which is responsible for ensuring coherency between processors, and I/O coherency between processors and the DMA-capable devices), a mistake was made: the CPU0-specific registers were specified instead of the virtual CPU registers. This means that the coherency barrier needed for I/O coherency was not behaving properly when executed from a CPU different from CPU0. This patch fixes that by using the virtual CPU registers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8+ Fixes: e60304f8cb "arm: mvebu: Add hardware I/O Coherency support" Signed-off-by: Jason Cooper <jason@lakedaemon.net>		2013-11-25 18:22:10 +00:00
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bootp
compressed	Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm	2013-11-14 08:51:29 +09:00
dts	ARM: mvebu: use the virtual CPU registers to access coherency registers	2013-11-25 18:22:10 +00:00
.gitignore
install.sh	arm, kbuild: make "make install" not depend on vmlinux	2013-10-02 22:30:35 +02:00
Makefile	arm, kbuild: make "make install" not depend on vmlinux	2013-10-02 22:30:35 +02:00