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433c858a61
This code was reworked in commit,
905e75c46d
This change removed the fsl_add_bridge() which originally was above
the addition of the pci_exclude_device function. I think the assumption was that
the pci_exclude_device would prevent changes to the bridge PCI config after
it's been added. It seems it wasn't fully tested on MPC85xx ADS because
if you move the fsl_add_bridge() the pci_exclude_device is set in the machine
description then you can never update the PCI Config since the exclude
prevents it. This disrupts things like DMA.
This issue was extensively debugged by David Beazley.
Cc: xe-kernel@external.cisco.com
Cc: dbeazley@cisco.com
Cc: dwalker@fifo99.com
Signed-off-by: Daniel Walker <danielwa@cisco.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
179 lines
4.9 KiB
C
179 lines
4.9 KiB
C
/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpic.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#ifdef CONFIG_CPM2
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#include <asm/cpm2.h>
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#include <sysdev/cpm2_pic.h>
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#endif
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#include "mpc85xx.h"
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static void __init mpc85xx_ads_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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mpc85xx_cpm2_pic_init();
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}
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/*
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* Setup the architecture
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*/
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#ifdef CONFIG_CPM2
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struct cpm_pin {
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int port, pin, flags;
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};
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static const struct cpm_pin mpc8560_ads_pins[] = {
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/* SCC1 */
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{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* SCC2 */
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{2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC2 */
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{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
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{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
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/* FCC3 */
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{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
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{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
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{2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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};
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static void __init init_ioports(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
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const struct cpm_pin *pin = &mpc8560_ads_pins[i];
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cpm2_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
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}
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#endif
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static void __init mpc85xx_ads_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
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#ifdef CONFIG_CPM2
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cpm2_reset();
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init_ioports();
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#endif
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fsl_pci_assign_primary();
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}
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static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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}
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machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_ads_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC85xxADS");
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}
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define_machine(mpc85xx_ads) {
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.name = "MPC85xx ADS",
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.probe = mpc85xx_ads_probe,
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.setup_arch = mpc85xx_ads_setup_arch,
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.init_IRQ = mpc85xx_ads_pic_init,
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.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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