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9a764234ee
Broadcom STB SoCs (brcmstb) require an early setup of their Bus Interface Unit control register, this needs to happen before SMP is brought up because it affects how the CPU complex will be interfaced to the memory controller. Add support code which properly initializes the BIU registers based on whether "brcm,write-pairing" is present in Device Tree, and take care of saving and restoring credit register settings during system-wide suspend/resume operations. Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
/*
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* Broadcom STB SoCs Bus Unit Interface controls
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*
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* Copyright (C) 2015, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#define CPU_CREDIT_REG_OFFSET 0x184
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#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
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static void __iomem *cpubiuctrl_base;
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static bool mcp_wr_pairing_en;
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static int __init mcp_write_pairing_set(void)
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{
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u32 creds = 0;
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if (!cpubiuctrl_base)
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return -1;
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creds = readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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if (mcp_wr_pairing_en) {
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pr_info("MCP: Enabling write pairing\n");
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writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
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pr_info("MCP: Disabling write pairing\n");
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writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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} else {
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pr_info("MCP: Write pairing already disabled\n");
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}
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return 0;
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}
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static int __init setup_hifcpubiuctrl_regs(void)
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{
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struct device_node *np;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
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if (!np) {
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pr_err("missing BIU control node\n");
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return -ENODEV;
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}
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cpubiuctrl_base = of_iomap(np, 0);
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if (!cpubiuctrl_base) {
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pr_err("failed to remap BIU control base\n");
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ret = -ENOMEM;
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goto out;
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}
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mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
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out:
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of_node_put(np);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static u32 cpu_credit_reg_dump; /* for save/restore */
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static int brcmstb_cpu_credit_reg_suspend(void)
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{
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if (cpubiuctrl_base)
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cpu_credit_reg_dump =
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readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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return 0;
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}
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static void brcmstb_cpu_credit_reg_resume(void)
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{
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if (cpubiuctrl_base)
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writel_relaxed(cpu_credit_reg_dump,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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}
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static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
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.suspend = brcmstb_cpu_credit_reg_suspend,
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.resume = brcmstb_cpu_credit_reg_resume,
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};
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#endif
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void __init brcmstb_biuctrl_init(void)
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{
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int ret;
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setup_hifcpubiuctrl_regs();
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ret = mcp_write_pairing_set();
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if (ret) {
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pr_err("MCP: Unable to disable write pairing!\n");
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return;
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}
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
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#endif
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}
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