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https://github.com/FEX-Emu/linux.git
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7808fa4853
This patch add multidrive support for pio driver Signed-off-by: Matteo Vit - Dave S.r.l. <matteo.vit@dave.eu> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
419 lines
8.4 KiB
C
419 lines
8.4 KiB
C
/*
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* Atmel PIO2 Port Multiplexer support
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/portmux.h>
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#include "pio.h"
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#define MAX_NR_PIO_DEVICES 8
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struct pio_device {
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void __iomem *regs;
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const struct platform_device *pdev;
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struct clk *clk;
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u32 pinmux_mask;
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u32 gpio_mask;
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char name[8];
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};
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static struct pio_device pio_dev[MAX_NR_PIO_DEVICES];
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static struct pio_device *gpio_to_pio(unsigned int gpio)
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{
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struct pio_device *pio;
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unsigned int index;
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index = gpio >> 5;
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if (index >= MAX_NR_PIO_DEVICES)
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return NULL;
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pio = &pio_dev[index];
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if (!pio->regs)
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return NULL;
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return pio;
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}
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/* Pin multiplexing API */
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void __init at32_select_periph(unsigned int pin, unsigned int periph,
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unsigned long flags)
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{
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struct pio_device *pio;
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unsigned int pin_index = pin & 0x1f;
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u32 mask = 1 << pin_index;
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pio = gpio_to_pio(pin);
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if (unlikely(!pio)) {
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printk("pio: invalid pin %u\n", pin);
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goto fail;
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}
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if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
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printk("%s: pin %u is busy\n", pio->name, pin_index);
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goto fail;
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}
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pio_writel(pio, PUER, mask);
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if (periph)
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pio_writel(pio, BSR, mask);
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else
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pio_writel(pio, ASR, mask);
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pio_writel(pio, PDR, mask);
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if (!(flags & AT32_GPIOF_PULLUP))
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pio_writel(pio, PUDR, mask);
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/* gpio_request NOT allowed */
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set_bit(pin_index, &pio->gpio_mask);
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return;
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fail:
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dump_stack();
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}
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void __init at32_select_gpio(unsigned int pin, unsigned long flags)
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{
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struct pio_device *pio;
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unsigned int pin_index = pin & 0x1f;
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u32 mask = 1 << pin_index;
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pio = gpio_to_pio(pin);
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if (unlikely(!pio)) {
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printk("pio: invalid pin %u\n", pin);
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goto fail;
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}
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if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
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printk("%s: pin %u is busy\n", pio->name, pin_index);
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goto fail;
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}
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if (flags & AT32_GPIOF_OUTPUT) {
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if (flags & AT32_GPIOF_HIGH)
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pio_writel(pio, SODR, mask);
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else
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pio_writel(pio, CODR, mask);
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if (flags & AT32_GPIOF_MULTIDRV)
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pio_writel(pio, MDER, mask);
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else
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pio_writel(pio, MDDR, mask);
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pio_writel(pio, PUDR, mask);
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pio_writel(pio, OER, mask);
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} else {
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if (flags & AT32_GPIOF_PULLUP)
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pio_writel(pio, PUER, mask);
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else
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pio_writel(pio, PUDR, mask);
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if (flags & AT32_GPIOF_DEGLITCH)
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pio_writel(pio, IFER, mask);
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else
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pio_writel(pio, IFDR, mask);
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pio_writel(pio, ODR, mask);
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}
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pio_writel(pio, PER, mask);
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/* gpio_request now allowed */
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clear_bit(pin_index, &pio->gpio_mask);
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return;
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fail:
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dump_stack();
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}
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/* Reserve a pin, preventing anyone else from changing its configuration. */
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void __init at32_reserve_pin(unsigned int pin)
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{
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struct pio_device *pio;
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unsigned int pin_index = pin & 0x1f;
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pio = gpio_to_pio(pin);
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if (unlikely(!pio)) {
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printk("pio: invalid pin %u\n", pin);
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goto fail;
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}
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if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
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printk("%s: pin %u is busy\n", pio->name, pin_index);
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goto fail;
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}
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return;
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fail:
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dump_stack();
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}
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/*--------------------------------------------------------------------------*/
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/* GPIO API */
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int gpio_request(unsigned int gpio, const char *label)
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{
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struct pio_device *pio;
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unsigned int pin;
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pio = gpio_to_pio(gpio);
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if (!pio)
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return -ENODEV;
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pin = gpio & 0x1f;
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if (test_and_set_bit(pin, &pio->gpio_mask))
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return -EBUSY;
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return 0;
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}
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EXPORT_SYMBOL(gpio_request);
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void gpio_free(unsigned int gpio)
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{
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struct pio_device *pio;
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unsigned int pin;
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pio = gpio_to_pio(gpio);
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if (!pio) {
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printk(KERN_ERR
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"gpio: attempted to free invalid pin %u\n", gpio);
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return;
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}
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pin = gpio & 0x1f;
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if (!test_and_clear_bit(pin, &pio->gpio_mask))
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printk(KERN_ERR "gpio: freeing free or non-gpio pin %s-%u\n",
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pio->name, pin);
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}
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EXPORT_SYMBOL(gpio_free);
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int gpio_direction_input(unsigned int gpio)
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{
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struct pio_device *pio;
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unsigned int pin;
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pio = gpio_to_pio(gpio);
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if (!pio)
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return -ENODEV;
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pin = gpio & 0x1f;
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pio_writel(pio, ODR, 1 << pin);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned int gpio, int value)
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{
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struct pio_device *pio;
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unsigned int pin;
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pio = gpio_to_pio(gpio);
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if (!pio)
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return -ENODEV;
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gpio_set_value(gpio, value);
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pin = gpio & 0x1f;
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pio_writel(pio, OER, 1 << pin);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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int gpio_get_value(unsigned int gpio)
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{
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struct pio_device *pio = &pio_dev[gpio >> 5];
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return (pio_readl(pio, PDSR) >> (gpio & 0x1f)) & 1;
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}
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EXPORT_SYMBOL(gpio_get_value);
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void gpio_set_value(unsigned int gpio, int value)
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{
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struct pio_device *pio = &pio_dev[gpio >> 5];
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u32 mask;
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mask = 1 << (gpio & 0x1f);
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if (value)
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pio_writel(pio, SODR, mask);
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else
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pio_writel(pio, CODR, mask);
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}
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EXPORT_SYMBOL(gpio_set_value);
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/*--------------------------------------------------------------------------*/
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/* GPIO IRQ support */
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static void gpio_irq_mask(unsigned irq)
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{
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unsigned gpio = irq_to_gpio(irq);
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struct pio_device *pio = &pio_dev[gpio >> 5];
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pio_writel(pio, IDR, 1 << (gpio & 0x1f));
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}
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static void gpio_irq_unmask(unsigned irq)
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{
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unsigned gpio = irq_to_gpio(irq);
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struct pio_device *pio = &pio_dev[gpio >> 5];
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pio_writel(pio, IER, 1 << (gpio & 0x1f));
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}
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static int gpio_irq_type(unsigned irq, unsigned type)
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{
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if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip gpio_irqchip = {
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.name = "gpio",
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.mask = gpio_irq_mask,
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.unmask = gpio_irq_unmask,
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.set_type = gpio_irq_type,
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};
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static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct pio_device *pio = get_irq_chip_data(irq);
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unsigned gpio_irq;
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gpio_irq = (unsigned) get_irq_data(irq);
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for (;;) {
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u32 isr;
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struct irq_desc *d;
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/* ack pending GPIO interrupts */
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isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
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if (!isr)
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break;
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do {
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int i;
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i = ffs(isr) - 1;
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isr &= ~(1 << i);
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i += gpio_irq;
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d = &irq_desc[i];
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d->handle_irq(i, d);
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} while (isr);
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}
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}
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static void __init
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gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
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{
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unsigned i;
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set_irq_chip_data(irq, pio);
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set_irq_data(irq, (void *) gpio_irq);
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for (i = 0; i < 32; i++, gpio_irq++) {
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set_irq_chip_data(gpio_irq, pio);
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set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
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handle_simple_irq);
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}
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set_irq_chained_handler(irq, gpio_irq_handler);
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}
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/*--------------------------------------------------------------------------*/
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static int __init pio_probe(struct platform_device *pdev)
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{
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struct pio_device *pio = NULL;
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int irq = platform_get_irq(pdev, 0);
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int gpio_irq_base = GPIO_IRQ_BASE + pdev->id * 32;
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BUG_ON(pdev->id >= MAX_NR_PIO_DEVICES);
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pio = &pio_dev[pdev->id];
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BUG_ON(!pio->regs);
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gpio_irq_setup(pio, irq, gpio_irq_base);
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platform_set_drvdata(pdev, pio);
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printk(KERN_DEBUG "%s: base 0x%p, irq %d chains %d..%d\n",
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pio->name, pio->regs, irq, gpio_irq_base, gpio_irq_base + 31);
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return 0;
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}
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static struct platform_driver pio_driver = {
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.probe = pio_probe,
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.driver = {
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.name = "pio",
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},
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};
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static int __init pio_init(void)
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{
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return platform_driver_register(&pio_driver);
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}
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postcore_initcall(pio_init);
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void __init at32_init_pio(struct platform_device *pdev)
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{
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struct resource *regs;
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struct pio_device *pio;
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if (pdev->id > MAX_NR_PIO_DEVICES) {
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dev_err(&pdev->dev, "only %d PIO devices supported\n",
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MAX_NR_PIO_DEVICES);
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return;
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}
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pio = &pio_dev[pdev->id];
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snprintf(pio->name, sizeof(pio->name), "pio%d", pdev->id);
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs) {
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dev_err(&pdev->dev, "no mmio resource defined\n");
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return;
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}
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pio->clk = clk_get(&pdev->dev, "mck");
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if (IS_ERR(pio->clk))
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/*
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* This is a fatal error, but if we continue we might
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* be so lucky that we manage to initialize the
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* console and display this message...
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*/
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dev_err(&pdev->dev, "no mck clock defined\n");
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else
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clk_enable(pio->clk);
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pio->pdev = pdev;
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pio->regs = ioremap(regs->start, regs->end - regs->start + 1);
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/*
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* request_gpio() is only valid for pins that have been
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* explicitly configured as GPIO and not previously requested
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*/
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pio->gpio_mask = ~0UL;
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/* start with irqs disabled and acked */
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pio_writel(pio, IDR, ~0UL);
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(void) pio_readl(pio, ISR);
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}
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