Tony Luck c0b5a64d93 [IA64] Change default PSR.ac from '1' to '0' (Fix erratum #237) ... April 2014 Itanium processor specification update: http://www.intel.com/content/www/us/en/processors/itanium/itanium-specification-update.html describes this erratum: ========================================================================= 237. Under a complex set of conditions, store to load forwarding for a sub 8-byte load may complete incorrectly Problem: A load instruction may complete incorrectly when a code sequence using 4-byte or smaller load and store operations to the same address is executed in combination with specific timing of all the following concurrent conditions: store to load forwarding, alignment checking enabled, a mis-predicted branch, and complex cache utilization activity. Implication: The affected sub 8-byte instruction may complete incorrectly resulting in unpredictable system behavior. There is an extremely low probability of exposure due to the significant number of complex microarchitectural concurrent conditions required to encounter the erratum. Workaround: Set PSR.ac = 0 to completely avoid the erratum. Disabling Hyper-Threading will significantly reduce exposure to the conditions that contribute to encountering the erratum. Status: See the Summary Table of Changes for the affected steppings. ========================================================================= [Table of changes essentially lists all models from McKinley to Tukwila] The PSR.ac bit controls whether the processor will always generate an unaligned reference trap (0x5a00) for a misaligned data access (when PSR.ac=1) or if it will let the access succeed when running on a cpu that implements logic to handle some unaligned accesses. Way back in 2008 in commit b704882e70 [IA64] Rationalize kernel mode alignment checking we made the decision to always enable strict checking. We were already doing so in trap/interrupt context because the common preamble code set this bit - but the rest of supervisor code (and by inheritance user code) ran with PSR.ac=0. We now reverse that decision and set PSR.ac=0 everywhere in the kernel (also inherited by user processes). This will avoid the erratum using the method described in the Itanium specification update. Net effect for users is that the processor will handle unaligned access when it can (typically with a tiny performance bubble in the pipeline ... but much less invasive than taking a trap and having the OS perform the access). Signed-off-by: Tony Luck <tony.luck@intel.com>		2014-04-16 10:20:34 -07:00
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asm-offsets.c
irq.h
Kconfig	kvm: Allow build-time configuration of KVM device assignment	2013-04-28 12:58:56 +03:00
kvm_fw.c
kvm_lib.c
kvm_minstate.h
kvm-ia64.c	KVM: Use cond_resched() directly and remove useless kvm_resched()	2013-12-13 14:23:45 +01:00
lapic.h	KVM: Call common update function when ioapic entry changed.	2013-04-16 16:32:40 -03:00
Makefile	KVM: get rid of $(addprefix ../../../virt/kvm/, ...) in Makefiles	2013-05-19 15:14:00 +03:00
memcpy.S
memset.S
misc.h
mmio.c
optvfault.S
process.c
trampoline.S
vcpu.c
vcpu.h
vmm_ivt.S	[IA64] Change default PSR.ac from '1' to '0' (Fix erratum #237)	2014-04-16 10:20:34 -07:00
vmm.c	treewide: Put a space between #include and FILE	2012-06-28 11:44:36 +02:00
vti.h	KVM: ia64: fix sparse warnings	2011-05-22 08:39:57 -04:00
vtlb.c	Wrong asm register contraints in the kvm implementation	2013-03-19 16:14:54 -07:00