Thierry Reding c1d676cec5 clk: tegra: Use the proper parent for plld_dsi
The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10 16:04:22 +02:00
..
2015-02-15 11:11:47 -08:00
2015-02-17 09:27:54 -08:00
2015-02-19 20:58:42 -06:00
2015-02-17 09:27:54 -08:00
2015-02-15 10:48:44 -08:00
2015-02-12 09:16:56 -08:00
2015-02-18 09:05:48 -08:00
2015-02-15 10:48:44 -08:00
2015-02-18 08:01:44 -08:00
2015-02-18 09:43:46 -08:00
2015-02-17 09:38:59 -08:00
2015-02-15 10:24:55 -08:00
2015-02-18 08:40:29 +01:00
2015-02-18 09:05:48 -08:00
2015-02-21 19:16:42 -08:00
2015-02-17 09:38:59 -08:00
2015-02-15 10:24:55 -08:00
2015-02-11 10:28:45 -08:00