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78818e477b
Patch from Vitaly Wool This patch adds basic chip support for PNX4008 ARM platform. It's basically the same as the previous one, but with the rmk's comments taken into account. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
197 lines
4.9 KiB
ArmAsm
197 lines
4.9 KiB
ArmAsm
/*
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* linux/arch/arm/mach-pnx4008/sleep.S
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*
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* PNX4008 support for STOP mode and SDRAM self-refresh
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*
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* Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/hardware.h>
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#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
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#define PWR_CTRL_REG_OFFS 0x44
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#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
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#define MPMC_STATUS_REG_OFFS 0x4
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.text
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ENTRY(pnx4008_cpu_suspend)
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@this function should be entered in Direct run mode.
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@ save registers on stack
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stmfd sp!, {r0 - r6, lr}
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@ setup Power Manager base address in r4
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@ and put it's value in r5
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mov r4, #(PWRMAN_VA_BASE & 0xff000000)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
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ldr r5, [r4, #PWR_CTRL_REG_OFFS]
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@ setup SDRAM controller base address in r2
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@ and put it's value in r3
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mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
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ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
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@ clear SDRAM self-refresh bit latch
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and r5, r5, #(~(1 << 8))
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@ clear SDRAM self-refresh bit
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and r5, r5, #(~(1 << 9))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ do save current bit settings in r1
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mov r1, r5
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@ set SDRAM self-refresh bit
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orr r5, r5, #(1 << 9)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ set SDRAM self-refresh bit latch
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orr r5, r5, #(1 << 8)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ clear SDRAM self-refresh bit latch
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and r5, r5, #(~(1 << 8))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ clear SDRAM self-refresh bit
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and r5, r5, #(~(1 << 9))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ wait for SDRAM to get into self-refresh mode
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2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
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tst r3, #(1 << 2)
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beq 2b
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@ to prepare SDRAM to get out of self-refresh mode after wakeup
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orr r5, r5, #(1 << 7)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ do enter stop mode
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orr r5, r5, #(1 << 0)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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@ sleeping now...
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@ coming out of STOP mode into Direct Run mode
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@ clear STOP mode and SDRAM self-refresh bits
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str r1, [r4, #PWR_CTRL_REG_OFFS]
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@ wait for SDRAM to get out self-refresh mode
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3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
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tst r3, #5
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bne 3b
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@ restore regs and return
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ldmfd sp!, {r0 - r6, pc}
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ENTRY(pnx4008_cpu_suspend_sz)
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.word . - pnx4008_cpu_suspend
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ENTRY(pnx4008_cpu_standby)
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@ save registers on stack
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stmfd sp!, {r0 - r6, lr}
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@ setup Power Manager base address in r4
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@ and put it's value in r5
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mov r4, #(PWRMAN_VA_BASE & 0xff000000)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
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orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
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ldr r5, [r4, #PWR_CTRL_REG_OFFS]
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@ setup SDRAM controller base address in r2
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@ and put it's value in r3
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mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
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orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
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ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
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@ clear SDRAM self-refresh bit latch
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and r5, r5, #(~(1 << 8))
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@ clear SDRAM self-refresh bit
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and r5, r5, #(~(1 << 9))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ do save current bit settings in r1
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mov r1, r5
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@ set SDRAM self-refresh bit
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orr r5, r5, #(1 << 9)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ set SDRAM self-refresh bit latch
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orr r5, r5, #(1 << 8)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ clear SDRAM self-refresh bit latch
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and r5, r5, #(~(1 << 8))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ clear SDRAM self-refresh bit
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and r5, r5, #(~(1 << 9))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ wait for SDRAM to get into self-refresh mode
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2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
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tst r3, #(1 << 2)
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beq 2b
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@ set 'get out of self-refresh mode after wakeup' bit
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orr r5, r5, #(1 << 7)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now...
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@ set SDRAM self-refresh bit latch
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orr r5, r5, #(1 << 8)
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ clear SDRAM self-refresh bit latch
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and r5, r5, #(~(1 << 8))
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str r5, [r4, #PWR_CTRL_REG_OFFS]
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@ wait for SDRAM to get out self-refresh mode
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3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
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tst r3, #5
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bne 3b
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@ restore regs and return
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ldmfd sp!, {r0 - r6, pc}
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ENTRY(pnx4008_cpu_standby_sz)
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.word . - pnx4008_cpu_standby
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ENTRY(pnx4008_cache_clean_invalidate)
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stmfd sp!, {r0 - r6, lr}
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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ldmfd sp!, {r0 - r6, pc}
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