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426ab49b33
These GPIO bank offsets are useful when define a gpio number. E.G. when GPIO PORTC pin 6 is used for irq request pin of external expanding device, we can define it like: #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6) Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
125 lines
3.7 KiB
C
125 lines
3.7 KiB
C
/*
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_IOMUX_V3_H__
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#define __MACH_IOMUX_V3_H__
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/*
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* build IOMUX_PAD structure
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*
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* This iomux scheme is based around pads, which are the physical balls
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* on the processor.
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*
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* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
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* things like driving strength and pullup/pulldown.
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* - Each pad can have but not necessarily does have an output routing register
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* (IOMUXC_SW_MUX_CTL_PAD_x).
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* - Each pad can have but not necessarily does have an input routing register
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* (IOMUXC_x_SELECT_INPUT)
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*
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* The three register sets do not have a fixed offset to each other,
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* hence we order this table by pad control registers (which all pads
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* have) and put the optional i/o routing registers into additional
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* fields.
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*
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* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
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* If <padname> or <padmode> refers to a GPIO, it is named
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* GPIO_<unit>_<num>
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*
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*/
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struct pad_desc {
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unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */
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unsigned mux_mode:8;
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unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */
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#define NO_PAD_CTRL (1 << 16)
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unsigned pad_ctrl:17;
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unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */
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unsigned select_input:3;
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};
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#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
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_select_input, _pad_ctrl) \
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{ \
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.mux_ctrl_ofs = _mux_ctrl_ofs, \
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.mux_mode = _mux_mode, \
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.pad_ctrl_ofs = _pad_ctrl_ofs, \
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.pad_ctrl = _pad_ctrl, \
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.select_input_ofs = _select_input_ofs, \
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.select_input = _select_input, \
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}
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/*
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* Use to set PAD control
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*/
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#define PAD_CTL_DVS (1 << 13)
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#define PAD_CTL_HYS (1 << 8)
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#define PAD_CTL_PKE (1 << 7)
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#define PAD_CTL_PUE (1 << 6)
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#define PAD_CTL_PUS_100K_DOWN (0 << 4)
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#define PAD_CTL_PUS_47K_UP (1 << 4)
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#define PAD_CTL_PUS_100K_UP (2 << 4)
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#define PAD_CTL_PUS_22K_UP (3 << 4)
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#define PAD_CTL_ODE (1 << 3)
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#define PAD_CTL_DSE_LOW (0 << 1)
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#define PAD_CTL_DSE_MED (1 << 1)
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#define PAD_CTL_DSE_HIGH (2 << 1)
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#define PAD_CTL_DSE_MAX (3 << 1)
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#define PAD_CTL_SRE_FAST (1 << 0)
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#define PAD_CTL_SRE_SLOW (0 << 0)
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#define MX51_NUM_GPIO_PORT 4
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#define GPIO_PIN_MASK 0x1f
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#define GPIO_PORT_SHIFT 5
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#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
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#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
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#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
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#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
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#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
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#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
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#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
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/*
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* setups a single pad in the iomuxer
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*/
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int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
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/*
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* setups mutliple pads
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* convenient way to call the above function with tables
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*/
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int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
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/*
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* Initialise the iomux controller
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*/
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void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
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#endif /* __MACH_IOMUX_V3_H__*/
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