Matthieu CASTET 5bf5dbeda2 usb: chipidea: need to mask when writting endptflush and endptprime ...

ENDPTFLUSH and ENDPTPRIME registers are set by software and clear
by hardware. There is a bit for each endpoint. When we are setting
a bit for an endpoint we should make sure we do not touch other
endpoint bit. There is a race condition if the hardware clear the
bit between the read and the write in hw_write.

Cc: stable <stable@vger.kernel.org> # 3.11+
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Tested-by: Michael Grzeschik <mgrzeschik@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2014-02-21 12:34:45 -08:00

..

bits.h

…

ci_hdrc_imx.c

usb: chipidea: imx: set CI_HDRC_IMX28_WRITE_FIX for imx28

2014-01-13 15:55:19 -08:00

ci_hdrc_imx.h

USB: chipidea: add guard macro to ci_hdrc_imx.h

2014-01-03 12:37:57 -08:00

ci_hdrc_msm.c

…

ci_hdrc_pci.c

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ci.h

usb: chipidea: add freescale imx28 special write register method

2014-01-13 15:55:19 -08:00

core.c

usb: chipidea: put hw_phymode_configure before ci_usb_phy_init

2014-01-13 15:55:19 -08:00

debug.c

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debug.h

…

host.c

usb: chipidea: add freescale imx28 special write register method

2014-01-13 15:55:19 -08:00

host.h

…

Kconfig

…

Makefile

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otg.c

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otg.h

usb: chipidea: need to mask INT_STATUS when write otgsc

2014-01-13 15:55:19 -08:00

udc.c

usb: chipidea: need to mask when writting endptflush and endptprime

2014-02-21 12:34:45 -08:00

udc.h

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usbmisc_imx.c

…