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c77cbdd11b
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>