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Winkle is a deep idle state supported in power8 chips. A core enters winkle when all the threads of the core enter winkle. In this state power supply to the entire chiplet i.e core, private L2 and private L3 is turned off. As a result it gives higher powersavings compared to sleep. But entering winkle results in a total hypervisor state loss. Hence the hypervisor context has to be preserved before entering winkle and restored upon wake up. Power-on Reset Engine (PORE) is a dedicated engine which is responsible for powering on the chiplet during wake up. It can be programmed to restore the register contests of a few specific registers. This patch uses PORE to restore register state wherever possible and uses stack to save and restore rest of the necessary registers. With hypervisor state restore things fall under three categories- per-core state, per-subcore state and per-thread state. To manage this, extend the infrastructure introduced for sleep. Mainly we add a paca variable subcore_sibling_mask. Using this and the core_idle_state we can distingush first thread in core and subcore. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
212 lines
6.8 KiB
C
212 lines
6.8 KiB
C
/*
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* This control block defines the PACA which defines the processor
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* specific data for each logical processor on the system.
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* There are some pointers defined that are utilized by PLIC.
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*
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* C 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_PACA_H
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#define _ASM_POWERPC_PACA_H
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC64
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#include <asm/types.h>
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#include <asm/lppaca.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/exception-64e.h>
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#include <asm/kvm_book3s_asm.h>
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#endif
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register struct paca_struct *local_paca asm("r13");
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#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
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extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
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/*
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* Add standard checks that preemption cannot occur when using get_paca():
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* otherwise the paca_struct it points to may be the wrong one just after.
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*/
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#define get_paca() ((void) debug_smp_processor_id(), local_paca)
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#else
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#define get_paca() local_paca
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#endif
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#define get_lppaca() (get_paca()->lppaca_ptr)
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#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
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struct task_struct;
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/*
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* Defines the layout of the paca.
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*
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* This structure is not directly accessed by firmware or the service
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* processor.
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*/
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struct paca_struct {
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#ifdef CONFIG_PPC_BOOK3S
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/*
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* Because hw_cpu_id, unlike other paca fields, is accessed
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* routinely from other CPUs (from the IRQ code), we stick to
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* read-only (after boot) fields in the first cacheline to
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* avoid cacheline bouncing.
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*/
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struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
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#endif /* CONFIG_PPC_BOOK3S */
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/*
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* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
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* load lock_token and paca_index with a single lwz
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* instruction. They must travel together and be properly
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* aligned.
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*/
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#ifdef __BIG_ENDIAN__
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u16 lock_token; /* Constant 0x8000, used in locks */
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u16 paca_index; /* Logical processor number */
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#else
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u16 paca_index; /* Logical processor number */
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u16 lock_token; /* Constant 0x8000, used in locks */
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#endif
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u64 kernel_toc; /* Kernel TOC address */
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u64 kernelbase; /* Base address of kernel */
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u64 kernel_msr; /* MSR while running in kernel */
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void *emergency_sp; /* pointer to emergency stack */
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u64 data_offset; /* per cpu data offset */
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s16 hw_cpu_id; /* Physical processor number */
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u8 cpu_start; /* At startup, processor spins until */
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/* this becomes non-zero. */
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u8 kexec_state; /* set when kexec down has irqs off */
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#ifdef CONFIG_PPC_STD_MMU_64
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struct slb_shadow *slb_shadow_ptr;
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struct dtl_entry *dispatch_log;
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struct dtl_entry *dispatch_log_end;
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#endif /* CONFIG_PPC_STD_MMU_64 */
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u64 dscr_default; /* per-CPU default DSCR */
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#ifdef CONFIG_PPC_STD_MMU_64
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/*
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* Now, starting in cacheline 2, the exception save areas
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*/
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/* used for most interrupts/exceptions */
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u64 exgen[13] __attribute__((aligned(0x80)));
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u64 exmc[13]; /* used for machine checks */
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u64 exslb[13]; /* used for SLB/segment table misses
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* on the linear mapping */
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/* SLB related definitions */
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u16 vmalloc_sllp;
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u16 slb_cache_ptr;
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u32 slb_cache[SLB_CACHE_ENTRIES];
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#endif /* CONFIG_PPC_STD_MMU_64 */
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#ifdef CONFIG_PPC_BOOK3E
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u64 exgen[8] __attribute__((aligned(0x80)));
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/* Keep pgd in the same cacheline as the start of extlb */
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pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
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pgd_t *kernel_pgd; /* Kernel PGD */
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/* Shared by all threads of a core -- points to tcd of first thread */
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struct tlb_core_data *tcd_ptr;
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/*
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* We can have up to 3 levels of reentrancy in the TLB miss handler,
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* in each of four exception levels (normal, crit, mcheck, debug).
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*/
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u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
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u64 exmc[8]; /* used for machine checks */
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u64 excrit[8]; /* used for crit interrupts */
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u64 exdbg[8]; /* used for debug interrupts */
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/* Kernel stack pointers for use by special exceptions */
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void *mc_kstack;
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void *crit_kstack;
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void *dbg_kstack;
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struct tlb_core_data tcd;
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#endif /* CONFIG_PPC_BOOK3E */
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mm_context_t context;
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/*
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* then miscellaneous read-write fields
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*/
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struct task_struct *__current; /* Pointer to current */
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u64 kstack; /* Saved Kernel stack addr */
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u64 stab_rr; /* stab/slb round-robin counter */
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u64 saved_r1; /* r1 save for RTAS calls or PM */
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u64 saved_msr; /* MSR saved here by enter_rtas */
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u16 trap_save; /* Used when bad stack is encountered */
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u8 soft_enabled; /* irq soft-enable flag */
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u8 irq_happened; /* irq happened while soft-disabled */
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u8 io_sync; /* writel() needs spin_unlock sync */
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u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
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u8 nap_state_lost; /* NV GPR values lost in power7_idle */
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u64 sprg_vdso; /* Saved user-visible sprg */
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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u64 tm_scratch; /* TM scratch area for reclaim */
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#endif
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#ifdef CONFIG_PPC_POWERNV
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/* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
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u32 *core_idle_state_ptr;
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u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */
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/* Mask to indicate thread id in core */
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u8 thread_mask;
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/* Mask to denote subcore sibling threads */
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u8 subcore_sibling_mask;
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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/* Exclusive emergency stack pointer for machine check exception. */
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void *mc_emergency_sp;
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/*
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* Flag to check whether we are in machine check early handler
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* and already using emergency stack.
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*/
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u16 in_mce;
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u8 hmi_event_available; /* HMI event is available */
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#endif
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/* Stuff for accurate time accounting */
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u64 user_time; /* accumulated usermode TB ticks */
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u64 system_time; /* accumulated system TB ticks */
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u64 user_time_scaled; /* accumulated usermode SPURR ticks */
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u64 starttime; /* TB value snapshot */
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u64 starttime_user; /* TB value on exit to usermode */
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u64 startspurr; /* SPURR value snapshot */
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u64 utime_sspurr; /* ->user_time when ->startspurr set */
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u64 stolen_time; /* TB ticks taken by hypervisor */
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u64 dtl_ridx; /* read index in dispatch log */
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struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
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#ifdef CONFIG_KVM_BOOK3S_HANDLER
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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/* We use this to store guest state in */
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struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
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#endif
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struct kvmppc_host_state kvm_hstate;
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#endif
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};
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extern struct paca_struct *paca;
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extern void initialise_paca(struct paca_struct *new_paca, int cpu);
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extern void setup_paca(struct paca_struct *new_paca);
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extern void allocate_pacas(void);
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extern void free_unused_pacas(void);
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#else /* CONFIG_PPC64 */
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static inline void allocate_pacas(void) { };
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static inline void free_unused_pacas(void) { };
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#endif /* CONFIG_PPC64 */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PACA_H */
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