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1edc17832d
Davis S. Miller wrote: " The way we do that now is overkill. We only needed to use the MMU cache ops when we had sun4c around because sun4c lacked support for the "flush" instruction. But all sun4m and later chips have it so we can use it unconditionally. So in the per_cpu_patch() code, get rid of the cache ops invocation, and instead execute a "flush %reg" after each of the instruction patch assignments, where %reg is set to the address of the instruction that was stored into. Perhaps take the flushi() definition from asm/cacheflush_64.h and place it into asm/cacheflush.h, then you can simply use that. " Implemented as per suggestion. Moved run-time patching before we call paging_init(), so helper methods in paging_init() may utilise run-time patching too. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
13 lines
334 B
C
13 lines
334 B
C
#ifndef ___ASM_SPARC_CACHEFLUSH_H
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#define ___ASM_SPARC_CACHEFLUSH_H
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/* flush addr - to allow use of self-modifying code */
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#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
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#if defined(__sparc__) && defined(__arch64__)
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#include <asm/cacheflush_64.h>
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#else
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#include <asm/cacheflush_32.h>
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#endif
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#endif
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