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cbf09c8377
Currently for radix, flush_tlb_range flushes the entire PID, because the Linux mm code does not tell us about page size here for THP vs regular pages. This is quite sub-optimal for small mremap / mprotect / change_protection. So implement va range flushes with two flush passes, one for each page size (regular and THP). The second flush has an order of matnitude fewer tlbie instructions than the first, so it is a relatively small additional cost. There is still room for improvement here with some changes to generic APIs, particularly if there are mostly THP pages to be invalidated, the small page flushes could be reduced. Time to mprotect 1 page of memory (after mmap, touch): vanilla 2.9us 1.8us patched 1.2us 1.6us Time to mprotect 30 pages of memory (after mmap, touch): vanilla 8.2us 7.2us patched 6.9us 17.9us Time to mprotect 34 pages of memory (after mmap, touch): vanilla 9.1us 8.0us patched 9.0us 8.0us 34 pages is the point at which the invalidation switches from va to entire PID, which tlbie can do in a single instruction. This is why in the case of 30 pages, the new code runs slower for this test. This is a deliberate tradeoff already present in the unmap and THP promotion code, the idea is that the benefit from avoiding flushing entire TLB for this PID on all threads in the system. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
624 lines
17 KiB
C
624 lines
17 KiB
C
/*
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* TLB flush routines for radix kernels.
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*
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* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/memblock.h>
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#include <asm/ppc-opcode.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/trace.h>
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#include <asm/cputhreads.h>
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#define RIC_FLUSH_TLB 0
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#define RIC_FLUSH_PWC 1
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#define RIC_FLUSH_ALL 2
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static inline void __tlbiel_pid(unsigned long pid, int set,
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unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(53); /* IS = 1 */
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rb |= set << PPC_BITLSHIFT(51);
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rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 1, rb, rs, ric, prs, r);
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}
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/*
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* We use 128 set in radix mode and 256 set in hpt mode.
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*/
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static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
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{
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int set;
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asm volatile("ptesync": : :"memory");
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/*
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* Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
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* also flush the entire Page Walk Cache.
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*/
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__tlbiel_pid(pid, 0, ric);
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/* For PWC, only one flush is needed */
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if (ric == RIC_FLUSH_PWC) {
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asm volatile("ptesync": : :"memory");
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return;
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}
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/* For the remaining sets, just flush the TLB */
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for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
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__tlbiel_pid(pid, set, RIC_FLUSH_TLB);
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
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}
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static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = PPC_BIT(53); /* IS = 1 */
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 1, rb, rs, ric, prs, r);
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}
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static inline void __tlbiel_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
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{
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unsigned long addr;
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unsigned long ap = mmu_get_ap(psize);
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for (addr = start; addr < end; addr += page_size)
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__tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
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}
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static inline void _tlbiel_va(unsigned long va, unsigned long pid,
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unsigned long psize, unsigned long ric)
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{
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unsigned long ap = mmu_get_ap(psize);
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asm volatile("ptesync": : :"memory");
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__tlbiel_va(va, pid, ap, ric);
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asm volatile("ptesync": : :"memory");
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}
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static inline void _tlbiel_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
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{
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asm volatile("ptesync": : :"memory");
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__tlbiel_va_range(start, end, pid, page_size, psize);
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asm volatile("ptesync": : :"memory");
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}
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static inline void __tlbie_va(unsigned long va, unsigned long pid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = pid << PPC_BITLSHIFT(31);
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prs = 1; /* process scoped */
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r = 1; /* raidx format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void __tlbie_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
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{
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unsigned long addr;
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unsigned long ap = mmu_get_ap(psize);
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for (addr = start; addr < end; addr += page_size)
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__tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
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}
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static inline void _tlbie_va(unsigned long va, unsigned long pid,
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unsigned long psize, unsigned long ric)
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{
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unsigned long ap = mmu_get_ap(psize);
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asm volatile("ptesync": : :"memory");
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__tlbie_va(va, pid, ap, ric);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbie_va_range(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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unsigned long psize)
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{
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asm volatile("ptesync": : :"memory");
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__tlbie_va_range(start, end, pid, page_size, psize);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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/*
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* Base TLB flushing operations:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes kernel pages
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*
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* - local_* variants of page and mm only apply to the current
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* processor
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*/
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void radix__local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_pid(pid, RIC_FLUSH_TLB);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__local_flush_tlb_mm);
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#ifndef CONFIG_SMP
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void radix__local_flush_all_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_pid(pid, RIC_FLUSH_ALL);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__local_flush_all_mm);
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#endif /* CONFIG_SMP */
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void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
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int psize)
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{
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unsigned long pid;
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preempt_disable();
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pid = mm->context.id;
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if (pid != MMU_NO_CONTEXT)
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_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
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preempt_enable();
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}
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void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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/* need the return fix for nohash.c */
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if (is_vm_hugetlb_page(vma))
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return radix__local_flush_hugetlb_page(vma, vmaddr);
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#endif
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radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, mmu_virtual_psize);
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}
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EXPORT_SYMBOL(radix__local_flush_tlb_page);
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#ifdef CONFIG_SMP
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void radix__flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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return;
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preempt_disable();
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if (!mm_is_thread_local(mm))
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_tlbie_pid(pid, RIC_FLUSH_TLB);
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else
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_tlbiel_pid(pid, RIC_FLUSH_TLB);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__flush_tlb_mm);
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void radix__flush_all_mm(struct mm_struct *mm)
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{
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unsigned long pid;
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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return;
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preempt_disable();
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if (!mm_is_thread_local(mm))
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_tlbie_pid(pid, RIC_FLUSH_ALL);
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else
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_tlbiel_pid(pid, RIC_FLUSH_ALL);
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__flush_all_mm);
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void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
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{
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tlb->need_flush_all = 1;
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}
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EXPORT_SYMBOL(radix__flush_tlb_pwc);
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void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
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int psize)
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{
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unsigned long pid;
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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return;
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preempt_disable();
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if (!mm_is_thread_local(mm))
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_tlbie_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
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else
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_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
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preempt_enable();
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}
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void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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#ifdef CONFIG_HUGETLB_PAGE
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if (is_vm_hugetlb_page(vma))
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return radix__flush_hugetlb_page(vma, vmaddr);
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#endif
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radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, mmu_virtual_psize);
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}
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EXPORT_SYMBOL(radix__flush_tlb_page);
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#else /* CONFIG_SMP */
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#define radix__flush_all_mm radix__local_flush_all_mm
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#endif /* CONFIG_SMP */
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void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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_tlbie_pid(0, RIC_FLUSH_ALL);
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}
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EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
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#define TLB_FLUSH_ALL -1UL
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/*
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* Number of pages above which we invalidate the entire PID rather than
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* flush individual pages, for local and global flushes respectively.
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*
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* tlbie goes out to the interconnect and individual ops are more costly.
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* It also does not iterate over sets like the local tlbiel variant when
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* invalidating a full PID, so it has a far lower threshold to change from
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* individual page flushes to full-pid flushes.
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*/
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static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
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void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long pid;
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unsigned int page_shift = mmu_psize_defs[mmu_virtual_psize].shift;
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unsigned long page_size = 1UL << page_shift;
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unsigned long nr_pages = (end - start) >> page_shift;
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bool local, full;
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#ifdef CONFIG_HUGETLB_PAGE
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if (is_vm_hugetlb_page(vma))
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return radix__flush_hugetlb_tlb_range(vma, start, end);
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#endif
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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return;
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preempt_disable();
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local = mm_is_thread_local(mm);
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full = (end == TLB_FLUSH_ALL || nr_pages > tlb_single_page_flush_ceiling);
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if (full) {
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if (local)
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_tlbiel_pid(pid, RIC_FLUSH_TLB);
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else
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_tlbie_pid(pid, RIC_FLUSH_TLB);
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} else {
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bool hflush = false;
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unsigned long hstart, hend;
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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hstart = (start + HPAGE_PMD_SIZE - 1) >> HPAGE_PMD_SHIFT;
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hend = end >> HPAGE_PMD_SHIFT;
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if (hstart < hend) {
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hstart <<= HPAGE_PMD_SHIFT;
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hend <<= HPAGE_PMD_SHIFT;
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hflush = true;
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}
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#endif
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asm volatile("ptesync": : :"memory");
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if (local) {
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__tlbiel_va_range(start, end, pid, page_size, mmu_virtual_psize);
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if (hflush)
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__tlbiel_va_range(hstart, hend, pid,
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HPAGE_PMD_SIZE, MMU_PAGE_2M);
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asm volatile("ptesync": : :"memory");
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} else {
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__tlbie_va_range(start, end, pid, page_size, mmu_virtual_psize);
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if (hflush)
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__tlbie_va_range(hstart, hend, pid,
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HPAGE_PMD_SIZE, MMU_PAGE_2M);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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}
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preempt_enable();
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}
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EXPORT_SYMBOL(radix__flush_tlb_range);
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static int radix_get_mmu_psize(int page_size)
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{
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int psize;
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if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
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psize = mmu_virtual_psize;
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else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
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psize = MMU_PAGE_2M;
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else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
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psize = MMU_PAGE_1G;
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else
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return -1;
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return psize;
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}
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void radix__tlb_flush(struct mmu_gather *tlb)
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{
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int psize = 0;
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struct mm_struct *mm = tlb->mm;
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int page_size = tlb->page_size;
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psize = radix_get_mmu_psize(page_size);
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/*
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* if page size is not something we understand, do a full mm flush
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*
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* A "fullmm" flush must always do a flush_all_mm (RIC=2) flush
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* that flushes the process table entry cache upon process teardown.
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* See the comment for radix in arch_exit_mmap().
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*/
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if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
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radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
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else if (tlb->fullmm || tlb->need_flush_all) {
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tlb->need_flush_all = 0;
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radix__flush_all_mm(mm);
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} else
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radix__flush_tlb_mm(mm);
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}
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void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
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unsigned long end, int psize)
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{
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unsigned long pid;
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unsigned int page_shift = mmu_psize_defs[psize].shift;
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unsigned long page_size = 1UL << page_shift;
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unsigned long nr_pages = (end - start) >> page_shift;
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bool local, full;
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pid = mm->context.id;
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if (unlikely(pid == MMU_NO_CONTEXT))
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return;
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preempt_disable();
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local = mm_is_thread_local(mm);
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full = (end == TLB_FLUSH_ALL || nr_pages > tlb_single_page_flush_ceiling);
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if (full) {
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if (local)
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_tlbiel_pid(pid, RIC_FLUSH_TLB);
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else
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_tlbie_pid(pid, RIC_FLUSH_TLB);
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} else {
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if (local)
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_tlbiel_va_range(start, end, pid, page_size, psize);
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else
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_tlbie_va_range(start, end, pid, page_size, psize);
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}
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preempt_enable();
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}
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)
|
|
{
|
|
unsigned long pid, end;
|
|
|
|
pid = mm->context.id;
|
|
if (unlikely(pid == MMU_NO_CONTEXT))
|
|
return;
|
|
|
|
/* 4k page size, just blow the world */
|
|
if (PAGE_SIZE == 0x1000) {
|
|
radix__flush_all_mm(mm);
|
|
return;
|
|
}
|
|
|
|
end = addr + HPAGE_PMD_SIZE;
|
|
|
|
/* Otherwise first do the PWC, then iterate the pages. */
|
|
preempt_disable();
|
|
|
|
if (mm_is_thread_local(mm)) {
|
|
_tlbiel_pid(pid, RIC_FLUSH_PWC);
|
|
_tlbiel_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);
|
|
} else {
|
|
_tlbie_pid(pid, RIC_FLUSH_PWC);
|
|
_tlbie_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);
|
|
}
|
|
|
|
preempt_enable();
|
|
}
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
|
|
|
void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
|
|
unsigned long page_size)
|
|
{
|
|
unsigned long rb,rs,prs,r;
|
|
unsigned long ap;
|
|
unsigned long ric = RIC_FLUSH_TLB;
|
|
|
|
ap = mmu_get_ap(radix_get_mmu_psize(page_size));
|
|
rb = gpa & ~(PPC_BITMASK(52, 63));
|
|
rb |= ap << PPC_BITLSHIFT(58);
|
|
rs = lpid & ((1UL << 32) - 1);
|
|
prs = 0; /* process scoped */
|
|
r = 1; /* raidx format */
|
|
|
|
asm volatile("ptesync": : :"memory");
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
|
|
asm volatile("eieio; tlbsync; ptesync": : :"memory");
|
|
trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
|
|
}
|
|
EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
|
|
|
|
void radix__flush_tlb_lpid(unsigned long lpid)
|
|
{
|
|
unsigned long rb,rs,prs,r;
|
|
unsigned long ric = RIC_FLUSH_ALL;
|
|
|
|
rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
|
|
rs = lpid & ((1UL << 32) - 1);
|
|
prs = 0; /* partition scoped */
|
|
r = 1; /* raidx format */
|
|
|
|
asm volatile("ptesync": : :"memory");
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
|
|
asm volatile("eieio; tlbsync; ptesync": : :"memory");
|
|
trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
|
|
}
|
|
EXPORT_SYMBOL(radix__flush_tlb_lpid);
|
|
|
|
void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
|
|
unsigned long start, unsigned long end)
|
|
{
|
|
radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
|
|
}
|
|
EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
|
|
|
|
void radix__flush_tlb_all(void)
|
|
{
|
|
unsigned long rb,prs,r,rs;
|
|
unsigned long ric = RIC_FLUSH_ALL;
|
|
|
|
rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
|
|
prs = 0; /* partition scoped */
|
|
r = 1; /* raidx format */
|
|
rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
|
|
|
|
asm volatile("ptesync": : :"memory");
|
|
/*
|
|
* now flush guest entries by passing PRS = 1 and LPID != 0
|
|
*/
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
|
|
trace_tlbie(0, 0, rb, rs, ric, prs, r);
|
|
/*
|
|
* now flush host entires by passing PRS = 0 and LPID == 0
|
|
*/
|
|
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
|
|
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
|
|
asm volatile("eieio; tlbsync; ptesync": : :"memory");
|
|
trace_tlbie(0, 0, rb, 0, ric, prs, r);
|
|
}
|
|
|
|
void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
|
|
unsigned long address)
|
|
{
|
|
/*
|
|
* We track page size in pte only for DD1, So we can
|
|
* call this only on DD1.
|
|
*/
|
|
if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
|
|
VM_WARN_ON(1);
|
|
return;
|
|
}
|
|
|
|
if (old_pte & R_PAGE_LARGE)
|
|
radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
|
|
else
|
|
radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
|
|
}
|
|
|
|
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
|
|
extern void radix_kvm_prefetch_workaround(struct mm_struct *mm)
|
|
{
|
|
unsigned int pid = mm->context.id;
|
|
|
|
if (unlikely(pid == MMU_NO_CONTEXT))
|
|
return;
|
|
|
|
/*
|
|
* If this context hasn't run on that CPU before and KVM is
|
|
* around, there's a slim chance that the guest on another
|
|
* CPU just brought in obsolete translation into the TLB of
|
|
* this CPU due to a bad prefetch using the guest PID on
|
|
* the way into the hypervisor.
|
|
*
|
|
* We work around this here. If KVM is possible, we check if
|
|
* any sibling thread is in KVM. If it is, the window may exist
|
|
* and thus we flush that PID from the core.
|
|
*
|
|
* A potential future improvement would be to mark which PIDs
|
|
* have never been used on the system and avoid it if the PID
|
|
* is new and the process has no other cpumask bit set.
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_HVMODE) && radix_enabled()) {
|
|
int cpu = smp_processor_id();
|
|
int sib = cpu_first_thread_sibling(cpu);
|
|
bool flush = false;
|
|
|
|
for (; sib <= cpu_last_thread_sibling(cpu) && !flush; sib++) {
|
|
if (sib == cpu)
|
|
continue;
|
|
if (paca[sib].kvm_hstate.kvm_vcpu)
|
|
flush = true;
|
|
}
|
|
if (flush)
|
|
_tlbiel_pid(pid, RIC_FLUSH_ALL);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(radix_kvm_prefetch_workaround);
|
|
#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
|