Pavel Pisa b3c6b76ffb [ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-03-12 16:49:35 +00:00
..
2005-04-16 15:20:36 -07:00
2006-10-03 23:01:26 +02:00
2006-10-03 23:01:26 +02:00
2005-04-16 15:20:36 -07:00