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97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/*
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* Copyright (C) 2002 Momentum Computer, Inc.
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* Author: Matthew Dharm, mdharm@momenco.com
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*
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* Based on work by:
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status();
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if (pending & STATUSF_IP0)
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do_IRQ(0);
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else if (pending & STATUSF_IP1)
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do_IRQ(1);
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else if (pending & STATUSF_IP2)
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do_IRQ(2);
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else if (pending & STATUSF_IP3)
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do_IRQ(3);
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else if (pending & STATUSF_IP4)
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do_IRQ(4);
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else if (pending & STATUSF_IP5)
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do_IRQ(5);
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else if (pending & STATUSF_IP6)
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do_IRQ(6);
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else if (pending & STATUSF_IP7)
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ll_timer_interrupt(7);
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else {
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/*
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* Now look at the extended interrupts
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*/
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pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
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if (pending & STATUSF_IP8)
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ll_mv64340_irq();
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}
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}
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static struct irqaction cascade_mv64340 = {
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no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
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};
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void __init arch_init_irq(void)
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{
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/*
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* Clear all of the interrupts while we change the able around a bit.
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* int-handler is not on bootstrap
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*/
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clear_c0_status(ST0_IM);
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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/* set up the cascading interrupts */
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setup_irq(8, &cascade_mv64340);
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mv64340_irq_init(16);
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set_c0_status(ST0_IM);
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}
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