mirror of
https://github.com/FEX-Emu/linux.git
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6b5a12dbca
This branch is the culmination of 5 years of effort to bring the ARMv6 and ARMv7 platforms together such that they can all be enabled and boot the same kernel. It has been a tremendous amount of cleanup and refactoring by a huge number of people, and creation of several new (and major) subsystems to better abstract out all the platform details in an appropriate manner. The bulk of this branch is a large patchset from Arnd that brings several of the more minor and older platforms we have closer to multiplatform support. Among these are MMP, S3C64xx, Orion5x, mv78xx0 and realview Much of this is moving around header files from old mach directories, but there are also some cleanup patches of debug_ll (lowlevel debug per-platform options) and other parts. Linus Walleij also has some patchs to clean up the older ARM Realview platforms by finally introducing DT support, and Rob Herring has some for ARM Versatile which is now DT-only. Both of these platforms are now multiplatform. Finally, a couple of patches from Russell for Dove PMU, and a fix from Valentin Rothberg for Exynos ADC, which were rebased on top of the series to avoid conflicts. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIUAwUAVqAGcmCrR//JCVInAQLDog/4x9F0PHGmZhexGfFOpi2Od63Jjx55izRU zRXqRjjFjambOrZuOx8lEGDy/qzqKbsDU8D1P4IUugkDr2bLSXv+NTLZL1kNBIdm YOlJhw/BmzLYqauOHmBzGhtv1FDUk3rqbgTsP5tTWj5LpSkwjmqui3HBZpi+f3Rr YOn+NeQSARiw+51D0b106a9RFshQXRGgn5m3xFjLWhJqshb2z2Ew5cogX/zdwrrM ss1BFomxsvgk6S+snN6v7cEX2iXe3r89qNR5jEW5BgNpQGFsAUeXPr9zzH07L/Qq O7XLw9jt5MX/X5372zVHPb57WoflLbF9cFaaDUZV3eTqt3lC67BTxOtYIdC2i90k E5GYlsy88CRwT2EO+ok/6UTryph+hVv7JqHfbKfnISrbraMCK36DtDTpBIpZ9uYF rRB7ncJZUWBcyoe+qvitSl+2KV54iB1ez2RXsketxM98dDZsfB2M2ImFou1F/Pgg ALvpifPubi/uDe7xNUsSuaT6/3jAomBuNsxnkYJ3NeiH/+duZbOYGkzK/LlcjZyc UrA0IpLfwIFsBNzwfpZPZ1lkEu8Y1YZZ+Hv9k65q1wMuBDgrFI5zUeYrPZi4pN9T Yo1xP9FstVLDouJrpGZo12VIIxR1UBeGqfRI/BZ58LEF3PRq/g2OVFsdQia5gZKr ddiJKSL1Vw== =z1AW -----END PGP SIGNATURE----- Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform code updates from Arnd Bergmann: "This branch is the culmination of 5 years of effort to bring the ARMv6 and ARMv7 platforms together such that they can all be enabled and boot the same kernel. It has been a tremendous amount of cleanup and refactoring by a huge number of people, and creation of several new (and major) subsystems to better abstract out all the platform details in an appropriate manner. The bulk of this branch is a large patchset from Arnd that brings several of the more minor and older platforms we have closer to multiplatform support. Among these are MMP, S3C64xx, Orion5x, mv78xx0 and realview Much of this is moving around header files from old mach directories, but there are also some cleanup patches of debug_ll (lowlevel debug per-platform options) and other parts. Linus Walleij also has some patchs to clean up the older ARM Realview platforms by finally introducing DT support, and Rob Herring has some for ARM Versatile which is now DT-only. Both of these platforms are now multiplatform. Finally, a couple of patches from Russell for Dove PMU, and a fix from Valentin Rothberg for Exynos ADC, which were rebased on top of the series to avoid conflicts" * tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits) ARM: realview: don't select SMP_ON_UP for UP builds ARM: s3c: simplify s3c_irqwake_{e,}intallow definition ARM: s3c64xx: fix pm-debug compilation iio: exynos-adc: fix irqf_oneshot.cocci warnings ARM: realview: build realview-dt SMP support only when used ARM: realview: select apropriate targets ARM: realview: clean up header files ARM: realview: make all header files local ARM: no longer make CPU targets visible separately ARM: integrator: use explicit core module options ARM: realview: enable multiplatform ARM: make default platform work for NOMMU ARM: debug-ll: move DEBUG_LL_UART_EFM32 to correct Kconfig location ARM: defconfig: use correct debug_ll settings ARM: versatile: convert to multi-platform ARM: versatile: merge mach code into a single file ARM: versatile: switch to DT only booting and remove legacy code ARM: versatile: add DT based PCI detection ARM: pxa: mark ezx structures as __maybe_unused ARM: pxa: mark raumfeld init functions as __maybe_unused ...
626 lines
15 KiB
C
626 lines
15 KiB
C
/*
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* arch/arm/mach-orion5x/ts78xx-setup.c
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*
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* Maintainer: Alexander Clouter <alex@digriz.org.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sysfs.h>
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#include <linux/platform_device.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/m48t86.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/timeriomem-rng.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "mpp.h"
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#include "orion5x.h"
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#include "ts78xx-fpga.h"
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/*****************************************************************************
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* TS-78xx Info
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****************************************************************************/
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/*
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* FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
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*/
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#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
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#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
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#define TS78XX_FPGA_REGS_SIZE SZ_1M
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static struct ts78xx_fpga_data ts78xx_fpga = {
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.id = 0,
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.state = 1,
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/* .supports = ... - populated by ts78xx_fpga_supports() */
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};
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc ts78xx_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
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.length = TS78XX_FPGA_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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static void __init ts78xx_map_io(void)
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{
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orion5x_map_io();
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iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
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}
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data ts78xx_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(0),
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};
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct mv_sata_platform_data ts78xx_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
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****************************************************************************/
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#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x808)
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#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE + 0x80c)
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static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
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{
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writeb(addr, TS_RTC_CTRL);
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return readb(TS_RTC_DATA);
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}
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static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr)
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{
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writeb(addr, TS_RTC_CTRL);
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writeb(value, TS_RTC_DATA);
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}
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static struct m48t86_ops ts78xx_ts_rtc_ops = {
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.readbyte = ts78xx_ts_rtc_readbyte,
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.writebyte = ts78xx_ts_rtc_writebyte,
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};
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static struct platform_device ts78xx_ts_rtc_device = {
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.name = "rtc-m48t86",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_rtc_ops,
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},
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.num_resources = 0,
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};
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/*
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* TS uses some of the user storage space on the RTC chip so see if it is
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* present; as it's an optional feature at purchase time and not all boards
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* will have it present
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*
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* I've used the method TS use in their rtc7800.c example for the detection
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*
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* TODO: track down a guinea pig without an RTC to see if we can work out a
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* better RTC detection routine
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*/
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static int ts78xx_ts_rtc_load(void)
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{
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int rc;
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unsigned char tmp_rtc0, tmp_rtc1;
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tmp_rtc0 = ts78xx_ts_rtc_readbyte(126);
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tmp_rtc1 = ts78xx_ts_rtc_readbyte(127);
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ts78xx_ts_rtc_writebyte(0x00, 126);
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ts78xx_ts_rtc_writebyte(0x55, 127);
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if (ts78xx_ts_rtc_readbyte(127) == 0x55) {
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ts78xx_ts_rtc_writebyte(0xaa, 127);
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if (ts78xx_ts_rtc_readbyte(127) == 0xaa
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&& ts78xx_ts_rtc_readbyte(126) == 0x00) {
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ts78xx_ts_rtc_writebyte(tmp_rtc0, 126);
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ts78xx_ts_rtc_writebyte(tmp_rtc1, 127);
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if (ts78xx_fpga.supports.ts_rtc.init == 0) {
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rc = platform_device_register(&ts78xx_ts_rtc_device);
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if (!rc)
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ts78xx_fpga.supports.ts_rtc.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_rtc_device);
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if (rc)
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pr_info("RTC could not be registered: %d\n",
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rc);
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return rc;
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}
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}
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pr_info("RTC not found\n");
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return -ENODEV;
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};
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static void ts78xx_ts_rtc_unload(void)
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{
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platform_device_del(&ts78xx_ts_rtc_device);
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}
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/*****************************************************************************
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* NAND Flash
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****************************************************************************/
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#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
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#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
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/*
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* hardware specific access to control-lines
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*
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* ctrl:
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* NAND_NCE: bit 0 -> bit 2
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* NAND_CLE: bit 1 -> bit 1
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* NAND_ALE: bit 2 -> bit 0
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*/
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static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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if (ctrl & NAND_CTRL_CHANGE) {
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unsigned char bits;
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bits = (ctrl & NAND_NCE) << 2;
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bits |= ctrl & NAND_CLE;
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bits |= (ctrl & NAND_ALE) >> 2;
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writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
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{
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return readb(TS_NAND_CTRL) & 0x20;
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}
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static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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void __iomem *io_base = chip->IO_ADDR_W;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min_t(int, 4 - off, len);
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writesb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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writesl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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writesb(io_base, buf, len);
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}
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static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
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uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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void __iomem *io_base = chip->IO_ADDR_R;
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unsigned long off = ((unsigned long)buf & 3);
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int sz;
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if (off) {
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sz = min_t(int, 4 - off, len);
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readsb(io_base, buf, sz);
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buf += sz;
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len -= sz;
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}
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sz = len >> 2;
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if (sz) {
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u32 *buf32 = (u32 *)buf;
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readsl(io_base, buf32, sz);
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buf += sz << 2;
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len -= sz << 2;
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}
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if (len)
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readsb(io_base, buf, len);
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}
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static struct mtd_partition ts78xx_ts_nand_parts[] = {
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{
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.name = "mbr",
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.offset = 0,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "initrd",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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}, {
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.name = "rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct platform_nand_data ts78xx_ts_nand_data = {
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.chip = {
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.nr_chips = 1,
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.partitions = ts78xx_ts_nand_parts,
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.nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
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.chip_delay = 15,
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.bbt_options = NAND_BBT_USE_FLASH,
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},
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.ctrl = {
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/*
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* The HW ECC offloading functions, used to give about a 9%
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* performance increase for 'dd if=/dev/mtdblockX' and 5% for
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* nanddump. This all however was changed by git commit
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* e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
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* no performance advantage to be had so we no longer bother
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*/
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.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
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.dev_ready = ts78xx_ts_nand_dev_ready,
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.write_buf = ts78xx_ts_nand_write_buf,
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.read_buf = ts78xx_ts_nand_read_buf,
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},
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};
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static struct resource ts78xx_ts_nand_resources
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= DEFINE_RES_MEM(TS_NAND_DATA, 4);
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static struct platform_device ts78xx_ts_nand_device = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_nand_data,
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},
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.resource = &ts78xx_ts_nand_resources,
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.num_resources = 1,
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};
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static int ts78xx_ts_nand_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_nand.init == 0) {
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rc = platform_device_register(&ts78xx_ts_nand_device);
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if (!rc)
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ts78xx_fpga.supports.ts_nand.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_nand_device);
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if (rc)
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pr_info("NAND could not be registered: %d\n", rc);
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return rc;
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};
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static void ts78xx_ts_nand_unload(void)
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{
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platform_device_del(&ts78xx_ts_nand_device);
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}
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/*****************************************************************************
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* HW RNG
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****************************************************************************/
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#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
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static struct resource ts78xx_ts_rng_resource
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= DEFINE_RES_MEM(TS_RNG_DATA, 4);
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static struct timeriomem_rng_data ts78xx_ts_rng_data = {
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.period = 1000000, /* one second */
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};
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static struct platform_device ts78xx_ts_rng_device = {
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.name = "timeriomem_rng",
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.id = -1,
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.dev = {
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.platform_data = &ts78xx_ts_rng_data,
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},
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.resource = &ts78xx_ts_rng_resource,
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.num_resources = 1,
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};
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static int ts78xx_ts_rng_load(void)
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{
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int rc;
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if (ts78xx_fpga.supports.ts_rng.init == 0) {
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rc = platform_device_register(&ts78xx_ts_rng_device);
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if (!rc)
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ts78xx_fpga.supports.ts_rng.init = 1;
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} else
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rc = platform_device_add(&ts78xx_ts_rng_device);
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if (rc)
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pr_info("RNG could not be registered: %d\n", rc);
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return rc;
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};
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static void ts78xx_ts_rng_unload(void)
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{
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platform_device_del(&ts78xx_ts_rng_device);
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}
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/*****************************************************************************
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* FPGA 'hotplug' support code
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****************************************************************************/
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static void ts78xx_fpga_devices_zero_init(void)
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{
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ts78xx_fpga.supports.ts_rtc.init = 0;
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ts78xx_fpga.supports.ts_nand.init = 0;
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ts78xx_fpga.supports.ts_rng.init = 0;
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}
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static void ts78xx_fpga_supports(void)
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{
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/* TODO: put this 'table' into ts78xx-fpga.h */
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switch (ts78xx_fpga.id) {
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case TS7800_REV_1:
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case TS7800_REV_2:
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case TS7800_REV_3:
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case TS7800_REV_4:
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case TS7800_REV_5:
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case TS7800_REV_6:
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case TS7800_REV_7:
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case TS7800_REV_8:
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case TS7800_REV_9:
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ts78xx_fpga.supports.ts_rtc.present = 1;
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ts78xx_fpga.supports.ts_nand.present = 1;
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ts78xx_fpga.supports.ts_rng.present = 1;
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break;
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default:
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/* enable devices if magic matches */
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switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
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case TS7800_FPGA_MAGIC:
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pr_warn("unrecognised FPGA revision 0x%.2x\n",
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ts78xx_fpga.id & 0xff);
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ts78xx_fpga.supports.ts_rtc.present = 1;
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ts78xx_fpga.supports.ts_nand.present = 1;
|
|
ts78xx_fpga.supports.ts_rng.present = 1;
|
|
break;
|
|
default:
|
|
ts78xx_fpga.supports.ts_rtc.present = 0;
|
|
ts78xx_fpga.supports.ts_nand.present = 0;
|
|
ts78xx_fpga.supports.ts_rng.present = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int ts78xx_fpga_load_devices(void)
|
|
{
|
|
int tmp, ret = 0;
|
|
|
|
if (ts78xx_fpga.supports.ts_rtc.present == 1) {
|
|
tmp = ts78xx_ts_rtc_load();
|
|
if (tmp)
|
|
ts78xx_fpga.supports.ts_rtc.present = 0;
|
|
ret |= tmp;
|
|
}
|
|
if (ts78xx_fpga.supports.ts_nand.present == 1) {
|
|
tmp = ts78xx_ts_nand_load();
|
|
if (tmp)
|
|
ts78xx_fpga.supports.ts_nand.present = 0;
|
|
ret |= tmp;
|
|
}
|
|
if (ts78xx_fpga.supports.ts_rng.present == 1) {
|
|
tmp = ts78xx_ts_rng_load();
|
|
if (tmp)
|
|
ts78xx_fpga.supports.ts_rng.present = 0;
|
|
ret |= tmp;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ts78xx_fpga_unload_devices(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (ts78xx_fpga.supports.ts_rtc.present == 1)
|
|
ts78xx_ts_rtc_unload();
|
|
if (ts78xx_fpga.supports.ts_nand.present == 1)
|
|
ts78xx_ts_nand_unload();
|
|
if (ts78xx_fpga.supports.ts_rng.present == 1)
|
|
ts78xx_ts_rng_unload();
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ts78xx_fpga_load(void)
|
|
{
|
|
ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
|
|
|
|
pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
|
|
(ts78xx_fpga.id >> 8) & 0xffffff,
|
|
ts78xx_fpga.id & 0xff);
|
|
|
|
ts78xx_fpga_supports();
|
|
|
|
if (ts78xx_fpga_load_devices()) {
|
|
ts78xx_fpga.state = -1;
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
};
|
|
|
|
static int ts78xx_fpga_unload(void)
|
|
{
|
|
unsigned int fpga_id;
|
|
|
|
fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
|
|
|
|
/*
|
|
* There does not seem to be a feasible way to block access to the GPIO
|
|
* pins from userspace (/dev/mem). This if clause should hopefully warn
|
|
* those foolish enough not to follow 'policy' :)
|
|
*
|
|
* UrJTAG SVN since r1381 can be used to reprogram the FPGA
|
|
*/
|
|
if (ts78xx_fpga.id != fpga_id) {
|
|
pr_err("FPGA magic/rev mismatch\n"
|
|
"TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
|
|
(ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
|
|
(fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
|
|
ts78xx_fpga.state = -1;
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (ts78xx_fpga_unload_devices()) {
|
|
ts78xx_fpga.state = -1;
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
};
|
|
|
|
static ssize_t ts78xx_fpga_show(struct kobject *kobj,
|
|
struct kobj_attribute *attr, char *buf)
|
|
{
|
|
if (ts78xx_fpga.state < 0)
|
|
return sprintf(buf, "borked\n");
|
|
|
|
return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
|
|
}
|
|
|
|
static ssize_t ts78xx_fpga_store(struct kobject *kobj,
|
|
struct kobj_attribute *attr, const char *buf, size_t n)
|
|
{
|
|
int value, ret;
|
|
|
|
if (ts78xx_fpga.state < 0) {
|
|
pr_err("FPGA borked, you must powercycle ASAP\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (strncmp(buf, "online", sizeof("online") - 1) == 0)
|
|
value = 1;
|
|
else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
|
|
value = 0;
|
|
else
|
|
return -EINVAL;
|
|
|
|
if (ts78xx_fpga.state == value)
|
|
return n;
|
|
|
|
ret = (ts78xx_fpga.state == 0)
|
|
? ts78xx_fpga_load()
|
|
: ts78xx_fpga_unload();
|
|
|
|
if (!(ret < 0))
|
|
ts78xx_fpga.state = value;
|
|
|
|
return n;
|
|
}
|
|
|
|
static struct kobj_attribute ts78xx_fpga_attr =
|
|
__ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
|
|
|
|
/*****************************************************************************
|
|
* General Setup
|
|
****************************************************************************/
|
|
static unsigned int ts78xx_mpp_modes[] __initdata = {
|
|
MPP0_UNUSED,
|
|
MPP1_GPIO, /* JTAG Clock */
|
|
MPP2_GPIO, /* JTAG Data In */
|
|
MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
|
|
MPP4_GPIO, /* JTAG Data Out */
|
|
MPP5_GPIO, /* JTAG TMS */
|
|
MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
|
|
MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
|
|
MPP8_UNUSED,
|
|
MPP9_UNUSED,
|
|
MPP10_UNUSED,
|
|
MPP11_UNUSED,
|
|
MPP12_UNUSED,
|
|
MPP13_UNUSED,
|
|
MPP14_UNUSED,
|
|
MPP15_UNUSED,
|
|
MPP16_UART,
|
|
MPP17_UART,
|
|
MPP18_UART,
|
|
MPP19_UART,
|
|
/*
|
|
* MPP[20] PCI Clock Out 1
|
|
* MPP[21] PCI Clock Out 0
|
|
* MPP[22] Unused
|
|
* MPP[23] Unused
|
|
* MPP[24] Unused
|
|
* MPP[25] Unused
|
|
*/
|
|
0,
|
|
};
|
|
|
|
static void __init ts78xx_init(void)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* Setup basic Orion functions. Need to be called early.
|
|
*/
|
|
orion5x_init();
|
|
|
|
orion5x_mpp_conf(ts78xx_mpp_modes);
|
|
|
|
/*
|
|
* Configure peripherals.
|
|
*/
|
|
orion5x_ehci0_init();
|
|
orion5x_ehci1_init();
|
|
orion5x_eth_init(&ts78xx_eth_data);
|
|
orion5x_sata_init(&ts78xx_sata_data);
|
|
orion5x_uart0_init();
|
|
orion5x_uart1_init();
|
|
orion5x_xor_init();
|
|
|
|
/* FPGA init */
|
|
ts78xx_fpga_devices_zero_init();
|
|
ret = ts78xx_fpga_load();
|
|
ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
|
|
if (ret)
|
|
pr_err("sysfs_create_file failed: %d\n", ret);
|
|
}
|
|
|
|
MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
|
|
/* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
|
|
.atag_offset = 0x100,
|
|
.nr_irqs = ORION5X_NR_IRQS,
|
|
.init_machine = ts78xx_init,
|
|
.map_io = ts78xx_map_io,
|
|
.init_early = orion5x_init_early,
|
|
.init_irq = orion5x_init_irq,
|
|
.init_time = orion5x_timer_init,
|
|
.restart = orion5x_restart,
|
|
MACHINE_END
|