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https://github.com/FEX-Emu/linux.git
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da252b8ee5
Move the boot vector setup code for the EMEV2 SoC to match the sh73a0 and r8a7779 implementations. With this in place all SoC specific SMP implementations for mach-shmobile uses the ->smp_prepare_cpus() callback to setup the boot vector. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* SMP support for Emma Mobile EV2
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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* Copyright (C) 2012 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <mach/emev2.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#define EMEV2_SCU_BASE 0x1e000000
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static DEFINE_SPINLOCK(scu_lock);
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static void __iomem *scu_base;
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static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
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{
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unsigned long tmp;
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/* we assume this code is running on a different cpu
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* than the one that is changing coherency setting */
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spin_lock(&scu_lock);
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tmp = readl(scu_base + 8);
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tmp &= ~clr;
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tmp |= set;
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writel(tmp, scu_base + 8);
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spin_unlock(&scu_lock);
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}
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static unsigned int __init emev2_get_core_count(void)
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{
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if (!scu_base) {
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scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
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emev2_clock_init(); /* need ioremapped SMU */
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}
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WARN_ON_ONCE(!scu_base);
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return scu_base ? scu_get_core_count(scu_base) : 1;
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}
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static void __cpuinit emev2_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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/* enable cache coherency */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu = cpu_logical_map(0);
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scu_enable(scu_base);
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/* Tell ROM loader about our vector (in headsmp.S) */
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emev2_set_boot_vector(__pa(shmobile_secondary_vector));
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/* enable cache coherency on CPU0 */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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}
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static void __init emev2_smp_init_cpus(void)
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{
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unsigned int ncores = emev2_get_core_count();
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shmobile_smp_init_cpus(ncores);
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}
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struct smp_operations emev2_smp_ops __initdata = {
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.smp_init_cpus = emev2_smp_init_cpus,
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.smp_prepare_cpus = emev2_smp_prepare_cpus,
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.smp_secondary_init = emev2_secondary_init,
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.smp_boot_secondary = emev2_boot_secondary,
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};
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