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The HSU DMA is developed to support High Speed UART controllers found in particular on Intel MID platforms such as Intel Medfield. The existing implementation is tighten to the drivers/tty/serial/mfd.c driver and has a lot of disadvantages. Besides that we would like to get rid of the old HS UART driver in regarding to extending the 8250 which supports generic DMAEngine API. That's why the current driver has been developed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
/*
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* Driver for the High Speed UART DMA
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*
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* Copyright (C) 2015 Intel Corporation
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*
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* Partially based on the bits found in drivers/tty/serial/mfd.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DMA_HSU_H__
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#define __DMA_HSU_H__
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#include <linux/spinlock.h>
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#include <linux/dma/hsu.h>
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#include "../virt-dma.h"
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#define HSU_CH_SR 0x00 /* channel status */
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#define HSU_CH_CR 0x04 /* channel control */
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#define HSU_CH_DCR 0x08 /* descriptor control */
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#define HSU_CH_BSR 0x10 /* FIFO buffer size */
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#define HSU_CH_MTSR 0x14 /* minimum transfer size */
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#define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */
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#define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */
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#define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
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#define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
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#define HSU_CH_D1SAR 0x28
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#define HSU_CH_D1TSR 0x2c
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#define HSU_CH_D2SAR 0x30
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#define HSU_CH_D2TSR 0x34
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#define HSU_CH_D3SAR 0x38
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#define HSU_CH_D3TSR 0x3c
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#define HSU_DMA_CHAN_NR_DESC 4
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#define HSU_DMA_CHAN_LENGTH 0x40
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/* Bits in HSU_CH_SR */
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#define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
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#define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8))
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#define HSU_CH_SR_CHE BIT(15)
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/* Bits in HSU_CH_CR */
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#define HSU_CH_CR_CHA BIT(0)
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#define HSU_CH_CR_CHD BIT(1)
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/* Bits in HSU_CH_DCR */
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#define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
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#define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
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#define HSU_CH_DCR_CHSOTO BIT(14)
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#define HSU_CH_DCR_CHSOE BIT(15)
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#define HSU_CH_DCR_CHDI(x) BIT(16 + (x))
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#define HSU_CH_DCR_CHEI BIT(23)
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#define HSU_CH_DCR_CHTOI(x) BIT(24 + (x))
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struct hsu_dma_sg {
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dma_addr_t addr;
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unsigned int len;
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};
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struct hsu_dma_desc {
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struct virt_dma_desc vdesc;
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enum dma_transfer_direction direction;
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struct hsu_dma_sg *sg;
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unsigned int nents;
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unsigned int active;
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enum dma_status status;
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};
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static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
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{
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return container_of(vdesc, struct hsu_dma_desc, vdesc);
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}
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struct hsu_dma_chan {
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struct virt_dma_chan vchan;
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void __iomem *reg;
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spinlock_t lock;
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/* hardware configuration */
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enum dma_transfer_direction direction;
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struct dma_slave_config config;
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struct hsu_dma_desc *desc;
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};
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static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct hsu_dma_chan, vchan.chan);
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}
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static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
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{
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return readl(hsuc->reg + offset);
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}
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static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
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u32 value)
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{
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writel(value, hsuc->reg + offset);
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}
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struct hsu_dma {
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struct dma_device dma;
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/* channels */
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struct hsu_dma_chan *chan;
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};
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static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
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{
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return container_of(ddev, struct hsu_dma, dma);
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}
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#endif /* __DMA_HSU_H__ */
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