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afddce0cc9
This is a fix for a bug introduced with commit
447cdf2628, submitted as archived here:
http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20080312235002.c717dde3.yoichi_yuasa%40tripeaks.co.jp
regrettably with no further explanation.
The issue is with the CP0 Count register read erratum present on R4000 and
some R4400 processors. If this erratum is present, then a read from this
register that happens around the time it reaches the value stored in the
CP0 Compare register causes a CP0 timer interrupt that is supposed to
happen when the values in the two registers match to be missed. The
implication for the chips affected is the CP0 timer can be used either as
a source of a timer interrupt (a clock event) or as a source of a
high-resolution counter (a clock source), but not both at a time.
The erratum does not affect timer interrupt operation itself, because in
this case the CP0 Count register is only read while the timer interrupt
has already been raised, while high-resolution counter references happen
at random times.
Additionally some systems apparently have issues with the timer interrupt
line being routed externally and not following the usual CP0 Count/Compare
semantics. In this case we don't want to use the R4k clock event.
We've meant to address the erratum and the timer interrupt routing issue
in time_init, however the commit referred to above broke our solution.
What we currently have is we enable the R4k clock source if the R4k clock
event initialization has succeeded (the timer is present and has no timer
interrupt routing issue) or there is no CP0 Count register read erratum.
Which gives the following boolean matrix:
clock event | count erratum => clock source
------------+---------------+--------------
0 | 0 | 1 (OK)
0 | 1 | 0 (bug!) -> no interference, could use
1 | 0 | 1 (OK)
1 | 1 | 1 (bug!) -> can't use, interference
What we want instead is to enable the R4k clock source if there is no CP0
Count register read erratum (obviously) or the R4k clock event
initialization has *failed* -- because in the latter case we won't be
using the timer interrupt anyway, so we don't care about any interference
CP0 Count reads might cause with the interrupt. This corresponds to the
following boolean matrix:
clock event | count erratum => clock source
------------+---------------+--------------
0 | 0 | 1
0 | 1 | 1
1 | 0 | 1
1 | 1 | 0
This is implemented here, effectively reverting the problematic commit,
and a short explanation is given next to code modified so that the
rationale is known to future readers and confusion is prevented from
happening here again.
It is worth noting that mips_clockevent_init returns 0 upon success while
cpu_has_mfc0_count_bug returns 0 upon failure. This is because the former
function returns an error code while the latter returns a boolean value.
To signify the difference I have therefore chosen to compare the result of
the former call explicitly against 0.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5799/
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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* Copyright (c) 2003, 2004 Maciej W. Rozycki
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*
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* Common time service routines for MIPS machines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/bug.h>
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#include <linux/clockchips.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/param.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <asm/cpu-features.h>
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#include <asm/div64.h>
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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/*
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* forward reference
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*/
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DEFINE_SPINLOCK(rtc_lock);
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EXPORT_SYMBOL(rtc_lock);
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int __weak rtc_mips_set_time(unsigned long sec)
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{
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return 0;
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}
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int __weak rtc_mips_set_mmss(unsigned long nowtime)
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{
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return rtc_mips_set_time(nowtime);
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}
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int update_persistent_clock(struct timespec now)
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{
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return rtc_mips_set_mmss(now.tv_sec);
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}
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static int null_perf_irq(void)
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{
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return 0;
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}
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int (*perf_irq)(void) = null_perf_irq;
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EXPORT_SYMBOL(perf_irq);
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/*
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* time_init() - it does the following things.
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*
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* 1) plat_time_init() -
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* a) (optional) set up RTC routines,
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* b) (optional) calibrate and set the mips_hpt_frequency
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* (only needed if you intended to use cpu counter as timer interrupt
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* source)
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* 2) calculate a couple of cached variables for later usage
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*/
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unsigned int mips_hpt_frequency;
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/*
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* This function exists in order to cause an error due to a duplicate
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* definition if platform code should have its own implementation. The hook
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* to use instead is plat_time_init. plat_time_init does not receive the
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* irqaction pointer argument anymore. This is because any function which
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* initializes an interrupt timer now takes care of its own request_irq rsp.
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* setup_irq calls and each clock_event_device should use its own
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* struct irqrequest.
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*/
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void __init plat_timer_setup(void)
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{
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BUG();
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}
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static __init int cpu_has_mfc0_count_bug(void)
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{
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switch (current_cpu_type()) {
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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/*
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* V3.0 is documented as suffering from the mfc0 from count bug.
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* Afaik this is the last version of the R4000. Later versions
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* were marketed as R4400.
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*/
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return 1;
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case CPU_R4400PC:
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case CPU_R4400SC:
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case CPU_R4400MC:
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/*
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* The published errata for the R4400 up to 3.0 say the CPU
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* has the mfc0 from count bug.
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*/
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if ((current_cpu_data.processor_id & 0xff) <= 0x30)
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return 1;
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/*
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* we assume newer revisions are ok
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*/
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return 0;
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}
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return 0;
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}
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void __init time_init(void)
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{
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plat_time_init();
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/*
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* The use of the R4k timer as a clock event takes precedence;
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* if reading the Count register might interfere with the timer
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* interrupt, then we don't use the timer as a clock source.
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* We may still use the timer as a clock source though if the
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* timer interrupt isn't reliable; the interference doesn't
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* matter then, because we don't use the interrupt.
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*/
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if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug())
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init_mips_clocksource();
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}
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