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1426d5a3bd
On 64-bit kernels we currently have a 512 byte struct paca_struct for each cpu (usually just called "the paca"). Currently they are statically allocated, which means a kernel built for a large number of cpus will waste a lot of space if it's booted on a machine with few cpus. We can avoid that by only allocating the number of pacas we need at boot. However this is complicated by the fact that we need to access the paca before we know how many cpus there are in the system. The solution is to dynamically allocate enough space for NR_CPUS pacas, but then later in boot when we know how many cpus we have, we free any unused pacas. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
300 lines
8.3 KiB
ArmAsm
300 lines
8.3 KiB
ArmAsm
/*
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* Low level routines for legacy iSeries support.
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*
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* Extracted from head_64.S
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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* This file contains the low-level support and setup for the
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* PowerPC-64 platform, including trap and interrupt dispatch.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/ptrace.h>
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#include <asm/cputable.h>
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#include "exception.h"
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.text
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.globl system_reset_iSeries
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system_reset_iSeries:
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bl .relative_toc
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mfspr r13,SPRN_SPRG3 /* Get alpaca address */
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LOAD_REG_ADDR(r23, alpaca)
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li r0,ALPACA_SIZE
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sub r23,r13,r23
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divdu r24,r23,r0 /* r24 has cpu number */
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cmpwi 0,r24,0 /* Are we processor 0? */
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bne 1f
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LOAD_REG_ADDR(r13, boot_paca)
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mtspr SPRN_SPRG_PACA,r13 /* Save it away for the future */
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mfmsr r23
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ori r23,r23,MSR_RI
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mtmsrd r23 /* RI on */
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b .__start_initialization_iSeries /* Start up the first processor */
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1: mfspr r4,SPRN_CTRLF
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li r5,CTRL_RUNLATCH /* Turn off the run light */
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andc r4,r4,r5
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mtspr SPRN_CTRLT,r4
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/* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
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/* In the UP case we'll yield() later, and we will not access the paca anyway */
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#ifdef CONFIG_SMP
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1:
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HMT_LOW
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LOAD_REG_ADDR(r23, __secondary_hold_spinloop)
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ld r23,0(r23)
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sync
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LOAD_REG_ADDR(r3,current_set)
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sldi r28,r24,3 /* get current_set[cpu#] */
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ldx r3,r3,r28
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addi r1,r3,THREAD_SIZE
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subi r1,r1,STACK_FRAME_OVERHEAD
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cmpwi 0,r23,0 /* Keep poking the Hypervisor until */
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bne 2f /* we're released */
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/* Let the Hypervisor know we are alive */
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/* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
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lis r3,0x8002
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rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
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li r0,-1 /* r0=-1 indicates a Hypervisor call */
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sc /* Invoke the hypervisor via a system call */
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b 1b
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#endif
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2:
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/* Load our paca now that it's been allocated */
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LOAD_REG_ADDR(r13, paca)
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ld r13,0(r13)
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mulli r0,r24,PACA_SIZE
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add r13,r13,r0
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mtspr SPRN_SPRG_PACA,r13 /* Save it away for the future */
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mfmsr r23
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ori r23,r23,MSR_RI
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mtmsrd r23 /* RI on */
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HMT_LOW
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#ifdef CONFIG_SMP
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lbz r23,PACAPROCSTART(r13) /* Test if this processor
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* should start */
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sync
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LOAD_REG_ADDR(r3,current_set)
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sldi r28,r24,3 /* get current_set[cpu#] */
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ldx r3,r3,r28
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addi r1,r3,THREAD_SIZE
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subi r1,r1,STACK_FRAME_OVERHEAD
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cmpwi 0,r23,0
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beq iSeries_secondary_smp_loop /* Loop until told to go */
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b __secondary_start /* Loop until told to go */
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iSeries_secondary_smp_loop:
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/* Let the Hypervisor know we are alive */
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/* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
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lis r3,0x8002
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rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
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#else /* CONFIG_SMP */
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/* Yield the processor. This is required for non-SMP kernels
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which are running on multi-threaded machines. */
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lis r3,0x8000
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rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
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addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
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li r4,0 /* "yield timed" */
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li r5,-1 /* "yield forever" */
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#endif /* CONFIG_SMP */
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li r0,-1 /* r0=-1 indicates a Hypervisor call */
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sc /* Invoke the hypervisor via a system call */
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mfspr r13,SPRN_SPRG_PACA /* Put r13 back ???? */
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b 2b /* If SMP not configured, secondaries
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* loop forever */
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/*** ISeries-LPAR interrupt handlers ***/
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STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
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.globl data_access_iSeries
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data_access_iSeries:
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mtspr SPRN_SPRG_SCRATCH0,r13
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BEGIN_FTR_SECTION
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mfspr r13,SPRN_SPRG_PACA
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std r9,PACA_EXSLB+EX_R9(r13)
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std r10,PACA_EXSLB+EX_R10(r13)
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mfspr r10,SPRN_DAR
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mfspr r9,SPRN_DSISR
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srdi r10,r10,60
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rlwimi r10,r9,16,0x20
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mfcr r9
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cmpwi r10,0x2c
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beq .do_stab_bolted_iSeries
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ld r10,PACA_EXSLB+EX_R10(r13)
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std r11,PACA_EXGEN+EX_R11(r13)
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ld r11,PACA_EXSLB+EX_R9(r13)
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std r12,PACA_EXGEN+EX_R12(r13)
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mfspr r12,SPRN_SPRG_SCRATCH0
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std r10,PACA_EXGEN+EX_R10(r13)
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std r11,PACA_EXGEN+EX_R9(r13)
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std r12,PACA_EXGEN+EX_R13(r13)
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EXCEPTION_PROLOG_ISERIES_1
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FTR_SECTION_ELSE
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EXCEPTION_PROLOG_1(PACA_EXGEN)
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EXCEPTION_PROLOG_ISERIES_1
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
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b data_access_common
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.do_stab_bolted_iSeries:
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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mfspr r10,SPRN_SPRG_SCRATCH0
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std r10,PACA_EXSLB+EX_R13(r13)
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EXCEPTION_PROLOG_ISERIES_1
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b .do_stab_bolted
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.globl data_access_slb_iSeries
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data_access_slb_iSeries:
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mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
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mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
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std r3,PACA_EXSLB+EX_R3(r13)
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mfspr r3,SPRN_DAR
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std r9,PACA_EXSLB+EX_R9(r13)
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mfcr r9
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#ifdef __DISABLED__
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cmpdi r3,0
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bge slb_miss_user_iseries
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#endif
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std r10,PACA_EXSLB+EX_R10(r13)
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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mfspr r10,SPRN_SPRG_SCRATCH0
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std r10,PACA_EXSLB+EX_R13(r13)
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ld r12,PACALPPACAPTR(r13)
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ld r12,LPPACASRR1(r12)
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b .slb_miss_realmode
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STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
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.globl instruction_access_slb_iSeries
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instruction_access_slb_iSeries:
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mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
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mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */
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std r3,PACA_EXSLB+EX_R3(r13)
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ld r3,PACALPPACAPTR(r13)
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ld r3,LPPACASRR0(r3) /* get SRR0 value */
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std r9,PACA_EXSLB+EX_R9(r13)
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mfcr r9
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#ifdef __DISABLED__
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cmpdi r3,0
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bge slb_miss_user_iseries
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#endif
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std r10,PACA_EXSLB+EX_R10(r13)
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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mfspr r10,SPRN_SPRG_SCRATCH0
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std r10,PACA_EXSLB+EX_R13(r13)
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ld r12,PACALPPACAPTR(r13)
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ld r12,LPPACASRR1(r12)
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b .slb_miss_realmode
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#ifdef __DISABLED__
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slb_miss_user_iseries:
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std r10,PACA_EXGEN+EX_R10(r13)
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std r11,PACA_EXGEN+EX_R11(r13)
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std r12,PACA_EXGEN+EX_R12(r13)
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mfspr r10,SPRG_SCRATCH0
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ld r11,PACA_EXSLB+EX_R9(r13)
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ld r12,PACA_EXSLB+EX_R3(r13)
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std r10,PACA_EXGEN+EX_R13(r13)
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std r11,PACA_EXGEN+EX_R9(r13)
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std r12,PACA_EXGEN+EX_R3(r13)
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EXCEPTION_PROLOG_ISERIES_1
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b slb_miss_user_common
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#endif
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MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
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STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
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STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
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STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
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MASKABLE_EXCEPTION_ISERIES(decrementer)
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STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
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STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
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.globl system_call_iSeries
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system_call_iSeries:
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mr r9,r13
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mfspr r13,SPRN_SPRG_PACA
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EXCEPTION_PROLOG_ISERIES_1
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b system_call_common
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STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
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STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
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STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
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decrementer_iSeries_masked:
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/* We may not have a valid TOC pointer in here. */
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li r11,1
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ld r12,PACALPPACAPTR(r13)
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stb r11,LPPACADECRINT(r12)
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LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
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lwz r12,0(r12)
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mtspr SPRN_DEC,r12
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/* fall through */
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hardware_interrupt_iSeries_masked:
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mtcrf 0x80,r9 /* Restore regs */
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ld r12,PACALPPACAPTR(r13)
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ld r11,LPPACASRR0(r12)
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ld r12,LPPACASRR1(r12)
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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ld r9,PACA_EXGEN+EX_R9(r13)
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ld r10,PACA_EXGEN+EX_R10(r13)
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ld r11,PACA_EXGEN+EX_R11(r13)
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ld r12,PACA_EXGEN+EX_R12(r13)
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ld r13,PACA_EXGEN+EX_R13(r13)
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rfid
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b . /* prevent speculative execution */
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_INIT_STATIC(__start_initialization_iSeries)
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/* Clear out the BSS */
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LOAD_REG_ADDR(r11,__bss_stop)
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LOAD_REG_ADDR(r8,__bss_start)
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sub r11,r11,r8 /* bss size */
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addi r11,r11,7 /* round up to an even double word */
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rldicl. r11,r11,61,3 /* shift right by 3 */
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beq 4f
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addi r8,r8,-8
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li r0,0
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mtctr r11 /* zero this many doublewords */
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3: stdu r0,8(r8)
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bdnz 3b
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4:
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LOAD_REG_ADDR(r1,init_thread_union)
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addi r1,r1,THREAD_SIZE
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li r0,0
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stdu r0,-STACK_FRAME_OVERHEAD(r1)
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bl .iSeries_early_setup
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bl .early_setup
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/* relocation is on at this point */
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b .start_here_common
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