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196f0082d8
Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
43 lines
2.0 KiB
Plaintext
43 lines
2.0 KiB
Plaintext
* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
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The OpenPIC specification does not specify which interrupt source has to
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become which interrupt number. This is up to the software implementation
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of the interrupt controller. The only requirement is that every
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interrupt source has to have an unique interrupt number / vector number.
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To accomplish this the current implementation assigns the number zero to
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the first source, the number one to the second source and so on until
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all interrupt sources have their unique number.
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Usually the assigned vector number equals the interrupt number mentioned
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in the documentation for a given core / CPU. This is however not true
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for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
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between internal and external interrupt sources and starts counting at
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zero for both of them.
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So what to write for external interrupt source X or internal interrupt
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source Y into the device tree? Here is an example:
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The memory map for the interrupt controller in the MPC8544[0] shows,
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that the first interrupt source starts at 0x5_0000 (PIC Register Address
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Map-Interrupt Source Configuration Registers). This source becomes the
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number zero therefore:
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External interrupt 0 = interrupt number 0
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External interrupt 1 = interrupt number 1
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External interrupt 2 = interrupt number 2
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...
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Every interrupt number allocates 0x20 bytes register space. So to get
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its number it is sufficient to shift the lower 16bits to right by five.
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So for the external interrupt 10 we have:
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0x0140 >> 5 = 10
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After the external sources, the internal sources follow. The in core I2C
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controller on the MPC8544 for instance has the internal source number
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27. Oo obtain its interrupt number we take the lower 16bits of its memory
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address (0x5_0560) and shift it right:
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0x0560 >> 5 = 43
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Therefore the I2C device node for the MPC8544 CPU has to have the
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interrupt number 43 specified in the device tree.
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[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
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MPC8544ERM Rev. 1 10/2007
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